{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,1]],"date-time":"2022-04-01T05:51:06Z","timestamp":1648792266282},"reference-count":10,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"7","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2017]]},"DOI":"10.1587\/elex.14.20161181","type":"journal-article","created":{"date-parts":[[2017,3,20]],"date-time":"2017-03-20T22:07:14Z","timestamp":1490047634000},"page":"20161181-20161181","source":"Crossref","is-referenced-by-count":1,"title":["Physical-aware gating element insertion for thermal-safe scan shift operation"],"prefix":"10.1587","volume":"14","author":[{"given":"Taehee","family":"Lee","sequence":"first","affiliation":[{"name":"System LSI, Samsung Electronics Co. Ltd."},{"name":"Department of Semiconductor and Display Engineering, Sungkyunkwan University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Joon-Sung","family":"Yang","sequence":"additional","affiliation":[{"name":"Department of Semiconductor and Display Engineering, Sungkyunkwan University"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"publisher","unstructured":"[1] M. M. Naeini and C. Y. Ooi: \u201cA novel scan architecture for low power scan-based testing,\u201d VLSI Des. <b>2015<\/b> (2015) 264071 (DOI: 10.1155\/2015\/264071).","DOI":"10.1155\/2015\/264071"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] Y. Lin, <i>et al.<\/i>: \u201cA transition isolation scan cell design for low shift and capture power,\u201d Asian Test Symposium (2012) 107 (DOI: 10.1109\/ATS.2012.29).","DOI":"10.1109\/ATS.2012.29"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] W. Zhao, <i>et al.<\/i>: \u201cPower-safe test application using an effective gating approach considering current limits,\u201d VLSI Test Symposium (2011) 160 (DOI: 10.1109\/VTS.2011.5783777).","DOI":"10.1109\/VTS.2011.5783777"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] R. Sankaralingam and N. A. Touba: \u201cInserting test points to control peak power during scan testing,\u201d IEEE International Symposium on defect and fault tolerance in VLSI systems (2002) 138 (DOI: 10.1109\/DFTVS.2002.1173510).","DOI":"10.1109\/DFTVS.2002.1173510"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] X. Lin and J. Rajski: \u201cTest power reduction by blocking scan cell outputs,\u201d Asian Test Symposium (2008) 329 (DOI: 10.1109\/ATS.2008.33).","DOI":"10.1109\/ATS.2008.33"},{"key":"6","doi-asserted-by":"publisher","unstructured":"[6] M. Elshoukryet al.: \u201cA critical path-aware partial gating approach for test power reduction,\u201d ACM Trans. Des. Autom. Electron. Syst. <b>12<\/b> (2007) 17 (DOI: 10.1145\/1230800.1230809).","DOI":"10.1145\/1230800.1230809"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] M. Elshoukry, <i>et al.<\/i>: \u201cPartial gating optimization for power reduction during test application,\u201d Asian Test Symposium (2005) 242 (DOI: 10.1109\/ATS.2005.87).","DOI":"10.1109\/ATS.2005.87"},{"key":"8","doi-asserted-by":"publisher","unstructured":"[8] X. Lin and Y. Huang: \u201cScan shift power reduction by freezing power sensitive scan cells,\u201d J. Electron. Test. <b>24<\/b> (2008) 327 (DOI: 10.1007\/s10836-007-5048-9).","DOI":"10.1007\/s10836-007-5048-9"},{"key":"9","doi-asserted-by":"publisher","unstructured":"[9] A. K. Suhaget al.: \u201cElimination of output gating performance overhead for critical paths in scan test,\u201d Int. J. Circuits Archit. Des. <b>1<\/b> (2013) 62 (DOI: 10.1504\/IJCAD.2013.057451).","DOI":"10.1504\/IJCAD.2013.057451"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] D. Jayaraman, <i>et al.<\/i>: \u201cGating internal nodes to reduce power during scan shift,\u201d Symposium on Great Lakes Symposium on VLSI (2010) 79 (DOI: 10.1145\/1785481.1785500).","DOI":"10.1145\/1785481.1785500"}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/14\/7\/14_14.20161181\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,25]],"date-time":"2017-06-25T13:04:27Z","timestamp":1498395867000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/14\/7\/14_14.20161181\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017]]},"references-count":10,"journal-issue":{"issue":"7","published-print":{"date-parts":[[2017]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.14.20161181","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2017]]}}}