{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,10]],"date-time":"2026-02-10T18:25:08Z","timestamp":1770747908979,"version":"3.49.0"},"reference-count":12,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"5","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2017]]},"DOI":"10.1587\/elex.14.20170027","type":"journal-article","created":{"date-parts":[[2017,2,14]],"date-time":"2017-02-14T17:08:20Z","timestamp":1487092100000},"page":"20170027-20170027","source":"Crossref","is-referenced-by-count":4,"title":["Impact of adjacent transistors on the SEU sensitivity of DICE flip-flop"],"prefix":"10.1587","volume":"14","author":[{"given":"Yang","family":"Li","sequence":"first","affiliation":[{"name":"School of Electronics and Information Engineering, Changchun University of Science and technology"}]},{"given":"Hua","family":"Cai","sequence":"additional","affiliation":[{"name":"School of Electronics and Information Engineering, Changchun University of Science and technology"}]},{"given":"Chen","family":"Xiaowen","sequence":"additional","affiliation":[{"name":"College of Computer, National University of Defense Technology"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"publisher","unstructured":"[1] D. Tanget al.: \u201cSoft error reliability in advanced CMOS technologies trends and challenges,\u201d Sci. China Technol. Sci. <b>57<\/b> (2014) 1846 (DOI: 10.1007\/s11431-014-5565-6).","DOI":"10.1007\/s11431-014-5565-6"},{"key":"2","unstructured":"[2] L. W. Massengill, <i>et al.<\/i>: \u201cTechnology scaling and soft error reliability,\u201d IRPS Papers (2012) 3.C.1 (DOI: 10.1109\/IRPS.2012.6241810)."},{"key":"3","doi-asserted-by":"publisher","unstructured":"[3] P. E. Doddet al.: \u201cProduction and propagation of single-event transients in high-speed digital logic ICs,\u201d IEEE Trans. Nucl. Sci. <b>51<\/b> (2004) 3278 (DOI: 10.1109\/TNS.2004.839172).","DOI":"10.1109\/TNS.2004.839172"},{"key":"4","doi-asserted-by":"publisher","unstructured":"[4] J. D. Blacket al.: \u201cPhysics of multiple-node charge collection and impacts on single-event characterization and soft error rate prediction,\u201d IEEE Trans. Nucl. Sci. <b>60<\/b> (2013) 1836 (DOI: 10.1109\/TNS.2013.2260357).","DOI":"10.1109\/TNS.2013.2260357"},{"key":"5","doi-asserted-by":"publisher","unstructured":"[5] X. Huiet al.: \u201cDICE-based test structure to measure the strength of charge sharing effect,\u201d IEICE Electron. Express <b>12<\/b> (2015) 20150629 (DOI: 10.1587\/elex.12.20150629).","DOI":"10.1587\/elex.12.20150629"},{"key":"6","doi-asserted-by":"publisher","unstructured":"[6] G. Gasiotet al.: \u201cExperimental soft error rate of several flip-flop designs representative of production chip in 32 nm CMOS technology,\u201d IEEE Trans. Nucl. Sci. <b>60<\/b> (2013) 4226 (DOI: 10.1109\/TNS.2013.2284546).","DOI":"10.1109\/TNS.2013.2284546"},{"key":"7","doi-asserted-by":"publisher","unstructured":"[7] X. Huiet al.: \u201cCircuit and layout combination technique to enhance multiple nodes upset tolerance in latches,\u201d IEICE Electron. Express <b>12<\/b> (2015) 20150286 (DOI: 10.1587\/elex.12.20150286).","DOI":"10.1587\/elex.12.20150286"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] T. Calinet al.: \u201cUpset hardened memory design for submicron CMOS technology,\u201d IEEE Trans. Nucl. Sci. <b>43<\/b> (1996) 2874 (DOI: 10.1109\/23.556880).","DOI":"10.1109\/23.556880"},{"key":"9","doi-asserted-by":"publisher","unstructured":"[9] O. A. Amusanet al.: \u201cCharge collection and charge sharing in a 130 nm CMOS technology,\u201d IEEE Trans. Nucl. Sci. <b>53<\/b> (2006) 3253 (DOI: 10.1109\/TNS.2006.884788).","DOI":"10.1109\/TNS.2006.884788"},{"key":"10","doi-asserted-by":"publisher","unstructured":"[10] R. Songet al.: \u201cPABAM: a physics-based analytical model to estimate bipolar amplification effect induced collected charge at circuit level,\u201d IEEE Trans. Device Mater. Rel. <b>15<\/b> (2015) 593 (DOI: 10.1109\/TDMR.2015.2490259).","DOI":"10.1109\/TDMR.2015.2490259"},{"key":"11","doi-asserted-by":"publisher","unstructured":"[11] R. Songet al.: \u201cFlip-flops soft error rate evaluation approach considering internal single-event transient,\u201d Sci. China Inf. Sci. <b>58<\/b> (2015) 062403 (DOI: 10.1007\/s11432-014-5260-z).","DOI":"10.1007\/s11432-014-5260-z"},{"key":"12","doi-asserted-by":"publisher","unstructured":"[12] B. Liang and R. Song: \u201cAnalyzing and mitigating the internal single-event transient in radiation hardened flip-flops at circuit-level,\u201d Sci. China Technol. Sci. <b>57<\/b> (2014) 1834 (DOI: 10.1007\/s11431-014-5595-0).","DOI":"10.1007\/s11431-014-5595-0"}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/14\/5\/14_14.20170027\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,25]],"date-time":"2017-06-25T06:32:29Z","timestamp":1498372349000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/14\/5\/14_14.20170027\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017]]},"references-count":12,"journal-issue":{"issue":"5","published-print":{"date-parts":[[2017]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.14.20170027","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2017]]}}}