{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,3]],"date-time":"2022-04-03T21:12:07Z","timestamp":1649020327230},"reference-count":10,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"5","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2017]]},"DOI":"10.1587\/elex.14.20170028","type":"journal-article","created":{"date-parts":[[2017,2,21]],"date-time":"2017-02-21T14:21:03Z","timestamp":1487686863000},"page":"20170028-20170028","source":"Crossref","is-referenced-by-count":0,"title":["Unified encoder embedded trellis router designs for decoding convolutional and turbo codes"],"prefix":"10.1587","volume":"14","author":[{"given":"Cheng-Hung","family":"Lin","sequence":"first","affiliation":[{"name":"Department of Electrical Engineering and Innovation Center for Big Data and Digital Convergence, Yuan Ze University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tsung-Ju","family":"Hsieh","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering and Innovation Center for Big Data and Digital Convergence, Yuan Ze University"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"publisher","unstructured":"[1] A. J. Viterbi: \u201cError bounds for convolutional codes and an asymptotically optimum decoding algorithm,\u201d IEEE Trans. Inf. Theory <b>13<\/b> (1967) 260 (DOI: 10.1109\/TIT.1967.1054010).","DOI":"10.1109\/TIT.1967.1054010"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] C. Berrou, <i>et al.<\/i>: \u201cNear Shannon limit error-correcting coding and decoding: Turbo-codes (1),\u201d Proc. IEEE Int. Conf. Commun. (1993) 1064 (DOI: 10.1109\/ICC.1993.397441).","DOI":"10.1109\/ICC.1993.397441"},{"key":"3","doi-asserted-by":"publisher","unstructured":"[3] C. Berrou and M. Jezequel: \u201cNon-binary convolutional codes for turbo coding,\u201d Electron. Lett. <b>35<\/b> (1999) 39 (DOI: 10.1049\/el:19990059).","DOI":"10.1049\/el:19990059"},{"key":"4","doi-asserted-by":"publisher","unstructured":"[4] B. M. Hochwald and S. ten Brink: \u201cAchieving near-capacity on a multiple-antenna channel,\u201d IEEE Trans. Commun. <b>51<\/b> (2003) 389 (DOI: 10.1109\/TCOMM.2003.809789).","DOI":"10.1109\/TCOMM.2003.809789"},{"key":"5","doi-asserted-by":"publisher","unstructured":"[5] F.-M. Liet al.: \u201cUnified convolutional\/turbo decoder design using tile-based timing analysis of VA\/MAP kernel,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>16<\/b> (2008) 1358 (DOI: 10.1109\/TVLSI.2008.2000514).","DOI":"10.1109\/TVLSI.2008.2000514"},{"key":"6","doi-asserted-by":"publisher","unstructured":"[6] C.-H. Linet al.: \u201cArea-efficient scalable MAP processor design for high-throughput multistandard convolutional turbo decoding,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>19<\/b> (2011) 305 (DOI: 10.1109\/TVLSI.2009.2032553).","DOI":"10.1109\/TVLSI.2009.2032553"},{"key":"7","doi-asserted-by":"publisher","unstructured":"[7] C.-H. Lin and C.-S. Yu: \u201cMultimode radix-4 SISO kernel design for turbo\/LDPC decoding,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>23<\/b> (2015) 2256 (DOI: 10.1109\/TVLSI.2014.2363777).","DOI":"10.1109\/TVLSI.2014.2363777"},{"key":"8","doi-asserted-by":"publisher","unstructured":"[8] C.-H. Linet al.: \u201cReconfigurable parallel turbo decoder design for multiple high-mobility 4G systems,\u201d J. Signal Process. Syst. <b>73<\/b> (2013) 109 (DOI: 10.1007\/s11265-013-0735-5).","DOI":"10.1007\/s11265-013-0735-5"},{"key":"9","doi-asserted-by":"publisher","unstructured":"[9] C.-C. Linet al.: \u201cDesign of a power-reduction Viterbi decoder for WLAN applications,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>52<\/b> (2005) 1148 (DOI: 10.1109\/TCSI.2005.849106).","DOI":"10.1109\/TCSI.2005.849106"},{"key":"10","doi-asserted-by":"publisher","unstructured":"[10] C. Studeret al.: \u201cDesign and implementation of a parallel turbo-decoder ASIC for 3GPP-LTE,\u201d IEEE J. Solid-State Circuits <b>46<\/b> (2011) 8 (DOI: 10.1109\/JSSC.2010.2075390).","DOI":"10.1109\/JSSC.2010.2075390"}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/14\/5\/14_14.20170028\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,25]],"date-time":"2017-06-25T11:01:34Z","timestamp":1498388494000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/14\/5\/14_14.20170028\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017]]},"references-count":10,"journal-issue":{"issue":"5","published-print":{"date-parts":[[2017]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.14.20170028","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2017]]}}}