{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,1]],"date-time":"2022-04-01T08:48:33Z","timestamp":1648802913262},"reference-count":13,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"5","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2017]]},"DOI":"10.1587\/elex.14.20170032","type":"journal-article","created":{"date-parts":[[2017,2,21]],"date-time":"2017-02-21T14:21:46Z","timestamp":1487686906000},"page":"20170032-20170032","source":"Crossref","is-referenced-by-count":2,"title":["Enhanced read performance for phase change memory using a reference column"],"prefix":"10.1587","volume":"14","author":[{"given":"Yu","family":"Lei","sequence":"first","affiliation":[{"name":"State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Houpeng","family":"Chen","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xi","family":"Li","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Qian","family":"Wang","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Qi","family":"Zhang","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jiajun","family":"Hu","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xiaoyun","family":"Li","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhen","family":"Tian","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhitang","family":"Song","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"publisher","unstructured":"[1] P. Junsangsri and F. Lombardi: \u201cA new comprehensive model of a phase change memory (PCM) cell,\u201d IEEE Trans. Nanotechnol. <b>13<\/b> (2014) 1213 (DOI: 10.1109\/TNANO.2014.2353992).","DOI":"10.1109\/TNANO.2014.2353992"},{"key":"2","doi-asserted-by":"publisher","unstructured":"[2] D. H. Jinet al.: \u201cA 15 \u00b5m-Pitch, 8.7-ENOB, 13-Mcells\/sec logarithmic readout circuit for multi-level cell phase change memory,\u201d IEEE J. Solid-State Circuits <b>50<\/b> (2015) 2431 (DOI: 10.1109\/JSSC.2015.2453236).","DOI":"10.1109\/JSSC.2015.2453236"},{"key":"3","doi-asserted-by":"publisher","unstructured":"[3] X. Liet al.: \u201cAn SPICE model for PCM based on Arrhenius equation,\u201d Chin. Phys. Lett. <b>26<\/b> (2009) 128501 (DOI: 10.1088\/0256-307X\/26\/12\/128501).","DOI":"10.1088\/0256-307X\/26\/12\/128501"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] Y. Choi, <i>et al.<\/i>: \u201cA 20 nm 1.8 V 8 Gb PRAM with 40 MB\/s program bandwidth,\u201d ISSCC Dig. Tech. Papers (2012) 46 (DOI: 10.1109\/ISSCC.2012.6176872).","DOI":"10.1109\/ISSCC.2012.6176872"},{"key":"5","doi-asserted-by":"publisher","unstructured":"[5] D. H. Wooet al.: \u201cPragmatic integration of an SRAM row cache in heterogeneous 3-D DRAM architecture using TSV,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>21<\/b> (2013) 1 (DOI: 10.1109\/TVLSI.2011.2176761).","DOI":"10.1109\/TVLSI.2011.2176761"},{"key":"6","doi-asserted-by":"publisher","unstructured":"[6] Q. Wanget al.: \u201cMethods to speed up read operation in a 64 Mbit phase change memory chip,\u201d IEICE Electron. Express <b>12<\/b> (2015) 20150792 (DOI: 10.1587\/elex.12.20150792).","DOI":"10.1587\/elex.12.20150792"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] S. Hanzawa, <i>et al.<\/i>: \u201cA 512 kB embedded phase change memory with 416 kB\/s write throughput at 100 \u00b5A cell write current,\u201d ISSCC Dig. Tech. Papers (2007) 474 (DOI: 10.1109\/ISSCC.2007.373500).","DOI":"10.1109\/ISSCC.2007.373500"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] K. Tsuchida, <i>et al.<\/i>: \u201cA 64 Mbit MRAM with clamped-reference and adequate-reference schemes,\u201d ISSCC Dig. Tech. Papers (2010) 258 (DOI: 10.1109\/ISSCC.2010.5433948).","DOI":"10.1109\/ISSCC.2010.5433948"},{"key":"9","doi-asserted-by":"publisher","unstructured":"[9] T. Andreet al.: \u201cA 4-Mb 0.18-\u00b5m 1T1MTJ toggle MRAM with balanced three input sensing scheme and locally mirrored unidirectional write drivers,\u201d IEEE J. Solid-State Circuits <b>40<\/b> (2005) 301 (DOI: 10.1109\/JSSC.2004.837962).","DOI":"10.1109\/JSSC.2004.837962"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] M. Chang, <i>et al.<\/i>: \u201c19.4 embedded 1 Mb ReRAM in 28 nm CMOS with 0.27-to-1 V read using swing-sample-and-couple sense amplifier and self-boost-write-termination scheme,\u201d ISSCC Dig. Tech. Papers (2014) 105 (DOI: 10.1109\/ISSCC.2014.6757457).","DOI":"10.1109\/ISSCC.2014.6757457"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] H. Lung, <i>et al.<\/i>: \u201cA double-data-rate 2 (DDR2) interface phase-change memory with 533 MB\/s read -write data rate and 37.5 ns access latency for memory-type storage class memory applications,\u201d IEEE International Memory Workshop (2016) (DOI: 10.1109\/IMW.2016.7493563).","DOI":"10.1109\/IMW.2016.7493563"},{"key":"12","doi-asserted-by":"publisher","unstructured":"[12] G. De Sandreet al.: \u201cA 4 Mb LV MOS-selected embedded phase change memory in 90 nm standard CMOS technology,\u201d IEEE J. Solid-State Circuits <b>46<\/b> (2011) 52 (DOI: 10.1109\/JSSC.2010.2084491).","DOI":"10.1109\/JSSC.2010.2084491"},{"key":"13","doi-asserted-by":"publisher","unstructured":"[13] X. Fanet al.: \u201cOptimization of periphery circuits in a 1 K-bit PCRAM chip for highly reliable write and read operations,\u201d IEICE Electron. Express <b>11<\/b> (2014) 20141071 (DOI: 10.1587\/elex.11.20141071).","DOI":"10.1587\/elex.11.20141071"}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/14\/5\/14_14.20170032\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,25]],"date-time":"2017-06-25T11:01:34Z","timestamp":1498388494000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/14\/5\/14_14.20170032\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017]]},"references-count":13,"journal-issue":{"issue":"5","published-print":{"date-parts":[[2017]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.14.20170032","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2017]]}}}