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Chaudhuri, <i>et al.<\/i>: \u201cIntroducing hierarchy-awareness in replacement and bypass algorithms for last-level caches,\u201d PACT (2012) 293 (DOI: 10.1145\/2370816.2370860)."},{"key":"7","unstructured":"[7] S. Das, <i>et al.<\/i>: \u201cSLIP: Reducing wire energy in the memory hierarchy,\u201d ISCA (2015) 349 (DOI: 10.1145\/2749469.2750398)."},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] J. Gaur, <i>et al.<\/i>: \u201cBypass and insertion algorithms for exclusive last-level caches,\u201d ISCA (2011) 81.","DOI":"10.1145\/2024723.2000075"},{"key":"9","unstructured":"[9] H. Liu, <i>et al.<\/i>: \u201cCache bursts: A new approach for eliminating dead blocks and increasing cache efficiency,\u201d MICRO (2008) 222 (DOI: 10.1109\/MICRO.2008.4771793)."},{"key":"10","unstructured":"[10] L. Xiang, <i>et al.<\/i>: \u201cLess reused filter: Improving l2 cache performance via filtering less reused lines,\u201d ICS (2009) 68 (DOI: 10.1145\/1542275.1542290)."},{"key":"11","unstructured":"[11] M. Kharbutli, <i>et al.<\/i>: \u201cSCIP: Selective cache insertion and bypassing to improve the performance of last-level caches,\u201d AEECT (2013) 1 (DOI: 10.1109\/AEECT.2013.6716445)."},{"key":"12","doi-asserted-by":"publisher","unstructured":"[12] W. Sritriratanaraket al.: \u201cApplying SVM to data bypass prediction in multi core last-level caches,\u201d IEICE Electron. Express <b>12<\/b> (2015) 20150736 (DOI: 10.1587\/elex.12.20150736).","DOI":"10.1587\/elex.12.20150736"},{"key":"13","doi-asserted-by":"publisher","unstructured":"[13] S. Mittal: \u201cA survey of cache bypassing techniques,\u201d J. Low Power Electron. Appl. <b>6<\/b> (2016) 5 (DOI: 10.3390\/jlpea6020005).","DOI":"10.3390\/jlpea6020005"},{"key":"14","unstructured":"[14] Q. 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