{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,5,17]],"date-time":"2023-05-17T04:42:15Z","timestamp":1684298535689},"reference-count":13,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"11","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2017]]},"DOI":"10.1587\/elex.14.20170353","type":"journal-article","created":{"date-parts":[[2017,5,14]],"date-time":"2017-05-14T22:11:00Z","timestamp":1494799860000},"page":"20170353-20170353","source":"Crossref","is-referenced-by-count":3,"title":["A metastability-immune error-resilient flip-flop for near-threshold variation-tolerant designs"],"prefix":"10.1587","volume":"14","author":[{"given":"Sheng","family":"Wang","sequence":"first","affiliation":[{"name":"Institute of VLSI Design, Zhejiang University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chen","family":"Chen","sequence":"additional","affiliation":[{"name":"State Key Laboratory of ASIC and System, Fudan University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xiaoyan","family":"Xiang","sequence":"additional","affiliation":[{"name":"State Key Laboratory of ASIC and System, Fudan University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jianyi","family":"Meng","sequence":"additional","affiliation":[{"name":"State Key Laboratory of ASIC and System, Fudan University"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"publisher","unstructured":"[1] X. Lianet al.: \u201cDynamic-static hybrid near-threshold-voltage adder design for ultra-low power applications,\u201d IEICE Electron. Express <b>12<\/b> (2015) 20141122 (DOI: 10.1587\/elex.12.20141122).","DOI":"10.1587\/elex.12.20141122"},{"key":"2","doi-asserted-by":"publisher","unstructured":"[2] W. Shanet al.: \u201cTiming monitoring paths selection for wide voltage IC,\u201d IEICE Electron. Express <b>13<\/b> (2016) 20160095 (DOI: 10.1587\/elex.13.20160095).","DOI":"10.1587\/elex.13.20160095"},{"key":"3","doi-asserted-by":"publisher","unstructured":"[3] S. Kim and M. Seok: \u201cVariation-tolerant, ultra-low-voltage microprocessor with a low-overhead, within-a-cycle in-situ timing-error detection and correction technique,\u201d IEEE J. Solid-State Circuits <b>50<\/b> (2015) 1478 (DOI: 10.1109\/JSSC.2015.2418713).","DOI":"10.1109\/JSSC.2015.2418713"},{"key":"4","doi-asserted-by":"publisher","unstructured":"[4] S. Daset al.: \u201cA self-tuning DVS processor using delay-error detection and correction,\u201d IEEE J. Solid-State Circuits <b>41<\/b> (2006) 792 (DOI: 10.1109\/JSSC.2006.870912).","DOI":"10.1109\/JSSC.2006.870912"},{"key":"5","doi-asserted-by":"publisher","unstructured":"[5] M. R. Choudhuryet al.: \u201cTime-borrowing circuit designs and hardware prototyping for timing error resilience,\u201d IEEE Trans. Comput. <b>63<\/b> (2014) 497 (DOI: 10.1109\/TC.2012.190).","DOI":"10.1109\/TC.2012.190"},{"key":"6","doi-asserted-by":"publisher","unstructured":"[6] M. Nejatet al.: \u201cDynamic flip-flop conversion: A time-borrowing method for performance improvement of low-power digital circuits prone to variations,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>23<\/b> (2015) 2724 (DOI: 10.1109\/TVLSI.2014.2366918).","DOI":"10.1109\/TVLSI.2014.2366918"},{"key":"7","doi-asserted-by":"publisher","unstructured":"[7] S. Valadimaset al.: \u201cTiming error tolerance in small core designs for SoC applications,\u201d IEEE Trans. Comput. <b>65<\/b> (2016) 654 (DOI: 10.1109\/TC.2015.2420562).","DOI":"10.1109\/TC.2015.2420562"},{"key":"8","doi-asserted-by":"publisher","unstructured":"[8] I. Kwonet al.: \u201cRazor-lite: A light-weight register for error detection by observing virtual supply rails,\u201d IEEE J. Solid-State Circuits <b>49<\/b> (2014) 2054 (DOI: 10.1109\/JSSC.2014.2328658).","DOI":"10.1109\/JSSC.2014.2328658"},{"key":"9","doi-asserted-by":"publisher","unstructured":"[9] S. Daset al.: \u201cRazorII: In situ error detection and correction for PVT and SER tolerance,\u201d IEEE J. Solid-State Circuits <b>44<\/b> (2009) 32 (DOI: 10.1109\/JSSC.2008.2007145).","DOI":"10.1109\/JSSC.2008.2007145"},{"key":"10","doi-asserted-by":"publisher","unstructured":"[10] K. A. Bowmanet al.: \u201cEnergy-efficient and metastability-immune resilient circuits for dynamic variation tolerance,\u201d IEEE J. Solid-State Circuits <b>44<\/b> (2009) 49 (DOI: 10.1109\/JSSC.2008.2007148).","DOI":"10.1109\/JSSC.2008.2007148"},{"key":"11","doi-asserted-by":"publisher","unstructured":"[11] M. Fojtiket al.: \u201cBubble razor: Eliminating timing margins in an ARM cortex-M3 processor in 45 nm CMOS using architecturally independent error detection and correction,\u201d IEEE J. Solid-State Circuits <b>48<\/b> (2013) 66 (DOI: 10.1109\/JSSC.2012.2220912).","DOI":"10.1109\/JSSC.2012.2220912"},{"key":"12","unstructured":"[12] S. Valadimas, <i>et al.<\/i>: \u201cCost and power efficient timing error tolerance in flip-flop based microprocessor cores,\u201d Test Symposium (ETS) (2012) 1 (DOI: 10.1109\/ETS.2012.6233002)."},{"key":"13","unstructured":"[13] G. Sannena and B. P. Das: \u201cA metastability immune timing error masking flip-flop for dynamic variation tolerance,\u201d Great Lakes Symposium on VLSI (GLSVLSI) (2016) 151 (DOI: 10.1145\/2902961.2902976)."}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/14\/11\/14_14.20170353\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,10]],"date-time":"2017-06-10T03:29:03Z","timestamp":1497065343000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/14\/11\/14_14.20170353\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017]]},"references-count":13,"journal-issue":{"issue":"11","published-print":{"date-parts":[[2017]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.14.20170353","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2017]]}}}