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Quan, <i>et al.<\/i>: \u201cA 1.0625-to-14.025 Gb\/s multimedia transceiver with full-rate source-series-terminated transmit driver and floating-tap decision-feedback equalizer in 40 nm CMOS,\u201d ISSCC Dig. Tech. Papers (2011) 348 (DOI: 10.1109\/ISSCC.2011.5746348)."},{"key":"2","unstructured":"[2] S. D. Vamvakos, <i>et al.<\/i>: \u201cA 2.488\u201311.2 Gb\/s multi-protocol SerDes in 40 nm low-leakage CMOS for FPGA applications,\u201d IEEE MWSCAS (2012) 5 (DOI: 10.1109\/MWSCAS.2012.6291943)."},{"key":"3","doi-asserted-by":"publisher","unstructured":"[3] Z. Zhanget al.: \u201cA 2.4\u20133.6-GHz wideband subharmonically injection-locked PLL with adaptive injection timing alignment technique,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>25<\/b> (2017) 929 (DOI: 10.1109\/TVLSI.2016.2619362).","DOI":"10.1109\/TVLSI.2016.2619362"},{"key":"4","unstructured":"[4] X. Kuang and N. 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