{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,2,2]],"date-time":"2024-02-02T02:06:12Z","timestamp":1706839572341},"reference-count":19,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"11","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2017]]},"DOI":"10.1587\/elex.14.20170449","type":"journal-article","created":{"date-parts":[[2017,5,25]],"date-time":"2017-05-25T22:09:07Z","timestamp":1495750147000},"page":"20170449-20170449","source":"Crossref","is-referenced-by-count":1,"title":["Efficient AES cipher on coarse-grained reconfigurable architecture"],"prefix":"10.1587","volume":"14","author":[{"given":"Chao","family":"Wang","sequence":"first","affiliation":[{"name":"National ASIC System Engineering Research Center, Southeast University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Peng","family":"Cao","sequence":"additional","affiliation":[{"name":"National ASIC System Engineering Research Center, Southeast University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jun","family":"Yang","sequence":"additional","affiliation":[{"name":"National ASIC System Engineering Research Center, Southeast University"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","unstructured":"[1] NIST: Advanced encryption standard (AES) (Nov. 2001) http:\/\/csrc.nist.gov\/publications\/fips\/fips197\/fips-197.pdf."},{"key":"2","unstructured":"[2] NIST: Data encryption standard (DES) (Oct. 1999) http:\/\/csrc.nist.gov\/publications\/fips\/fips46-3\/fips46-3.pdf."},{"key":"3","doi-asserted-by":"publisher","unstructured":"[3] I. Verbauwhedeet al.: \u201cDesign and performance testing of a 2.29 gb\/s Rijndael processor,\u201d IEEE J. Solid-State Circuits <b>38<\/b> (2003) 569 (DOI: 10.1109\/JSSC.2002.808300).","DOI":"10.1109\/JSSC.2002.808300"},{"key":"4","doi-asserted-by":"publisher","unstructured":"[4] A. Hodjat and I. Verbauwhede: \u201cArea-throughput trade-offs for fully pipelined 30 to 70 Gbits\/s AES processors,\u201d IEEE Trans. Comput. <b>55<\/b> (2006) 366 (DOI: 10.1109\/TC.2006.49).","DOI":"10.1109\/TC.2006.49"},{"key":"5","doi-asserted-by":"publisher","unstructured":"[5] S. Mathewet al.: \u201c340 mV\u20131.1 V, 289 Gbps\/W, 2090-gate NanoAES hardware accelerator with area-optimized encrypt\/decrypt GF(2<sup>4<\/sup>)<sup>2<\/sup> polynomials in 22 nm tri-gate CMOS,\u201d IEEE J. Solid-State Circuits <b>50<\/b> (2015) 1048 (DOI: 10.1109\/JSSC.2014.2384039).","DOI":"10.1109\/JSSC.2014.2384039"},{"key":"6","unstructured":"[6] Intel Corporation: Supplemental Streaming SIMD Extensions 3 (2012) http:\/\/en.wikipedia.org\/wiki\/SSSE3."},{"key":"7","unstructured":"[7] E. K\u00e4sper and P. Schwabe: \u201cFaster and timing-attack resistant AES-GCM,\u201d Proc. Int\u2019l Workshop Cryptographic Hardware and Embedded Systems (2009) 1 (DOI: 10.1007\/978-3-642-04138-9_1)."},{"key":"8","unstructured":"[8] Intel Corporation: Securing the Enterprise with Intel AES-NI (2010) http:\/\/www.intel.com\/content\/dam\/doc\/white-paper\/enterprise-security-aes-ni-white-paper.pdf."},{"key":"9","doi-asserted-by":"publisher","unstructured":"[9] N. Nishikawaet al.: \u201cHigh-performance symmetric block ciphers on multicore CPU and GPUs,\u201d Int. J. Netw. Comput. <b>2<\/b> (2012) 251 (DOI: 10.15803\/ijnc.2.2_251).","DOI":"10.15803\/ijnc.2.2_251"},{"key":"10","unstructured":"[10] S. A. Manavski: \u201cCUDA compatible GPU as an efficient hardware accelerator for AES cryptography,\u201d Proc. IEEE Int\u2019l Conf. Signal Processing and Comm. (2007) 65 (DOI: 10.1109\/ICSPC.2007.4728256)."},{"key":"11","unstructured":"[11] M. Patchappen, <i>et al.<\/i>: \u201cBatch processing of multi-variant AES cipher with GPU,\u201d Int\u2019l Conf. Computing Technology and Information Management (2015) 32 (DOI: 10.1109\/ICCTIM.2015.7224589)."},{"key":"12","doi-asserted-by":"publisher","unstructured":"[12] Z. Yuet al.: \u201cAsAP: An asynchronous array of simple processors,\u201d IEEE J. Solid-State Circuits <b>43<\/b> (2008) 695 (DOI: 10.1109\/JSSC.2007.916616).","DOI":"10.1109\/JSSC.2007.916616"},{"key":"13","doi-asserted-by":"publisher","unstructured":"[13] B. Liu and B. M. Baas: \u201cParallel AES encryption engines for many-core processor arrays,\u201d IEEE Trans. Comput. <b>62<\/b> (2013) 536 (DOI: 10.1109\/TC.2011.251).","DOI":"10.1109\/TC.2011.251"},{"key":"14","unstructured":"[14] A. Garcia, <i>et al.<\/i>: \u201cMapping of the AES cryptographic algorithm on a coarse-grain reconfigurable array processor,\u201d Int\u2019l Conf. Application-Specific Systems, Architectures and Processors (2008) 245 (DOI: 10.1109\/ASAP.2008.4580186)."},{"key":"15","unstructured":"[15] C. Mucci, <i>et al.<\/i>: \u201cImplementation of AES\/Rijndael on a dynamically reconfigurable architecture,\u201d Design, Automation and Test in Europe Conference and Exhibition (2007) 1 (DOI: 10.1109\/DATE.2007.364617)."},{"key":"16","unstructured":"[16] G. Sayilar and D. Chiou: \u201cCryptoraptor: High throughput reconfigurable cryptographic processor,\u201d IEEE\/ACM Int\u2019l Conf. Computer-Aided Design (2014) 155 (DOI: 10.1109\/ICCAD.2014.7001346)."},{"key":"17","doi-asserted-by":"publisher","unstructured":"[17] B. Liuet al.: \u201cReconfiguration process optimization of dynamically coarse grain reconfigurable architecture for multimedia applications,\u201d IEICE Trans. Inf. Syst. <b>E95-D<\/b> (2012) 1858 (DOI: 10.1587\/transinf.E95.D.1858).","DOI":"10.1587\/transinf.E95.D.1858"},{"key":"18","doi-asserted-by":"publisher","unstructured":"[18] Y. Wanget al.: \u201cOn-chip memory hierarchy in one coarse-grained reconfigurable architecture to compress memory space and to reduce reconfiguration time and data-reference time,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>22<\/b> (2014) 983 (DOI: 10.1109\/TVLSI.2013.2263155).","DOI":"10.1109\/TVLSI.2013.2263155"},{"key":"19","doi-asserted-by":"crossref","unstructured":"[19] M. Butler: \u201cAMD bulldozer CoreA new approach to multithreaded compute performance for maximum efficiency and throughput,\u201d Proc. IEEE HotChips Symp. (2010) 1.","DOI":"10.1109\/HOTCHIPS.2010.7480086"}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/14\/11\/14_14.20170449\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,9,25]],"date-time":"2019-09-25T04:18:29Z","timestamp":1569385109000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/14\/11\/14_14.20170449\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017]]},"references-count":19,"journal-issue":{"issue":"11","published-print":{"date-parts":[[2017]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.14.20170449","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2017]]}}}