{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,2]],"date-time":"2025-12-02T22:33:26Z","timestamp":1764714806444},"reference-count":16,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"13","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2017]]},"DOI":"10.1587\/elex.14.20170502","type":"journal-article","created":{"date-parts":[[2017,6,20]],"date-time":"2017-06-20T18:14:16Z","timestamp":1497982456000},"page":"20170502-20170502","source":"Crossref","is-referenced-by-count":4,"title":["A novel test data compression approach based on bit reversion"],"prefix":"10.1587","volume":"14","author":[{"given":"Shuo","family":"Cai","sequence":"first","affiliation":[{"name":"Hunan Provincial Key Laboratory of Intelligent Processing of Big Data on Transportation & College of Computer and Communication Engineering, Changsha University of Science and Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yinbo","family":"Zhou","sequence":"additional","affiliation":[{"name":"College of Information Science & Engineering, Hunan University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Peng","family":"Liu","sequence":"additional","affiliation":[{"name":"College of Information Science & Engineering, Hunan University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Fei","family":"Yu","sequence":"additional","affiliation":[{"name":"Hunan Provincial Key Laboratory of Intelligent Processing of Big Data on Transportation & College of Computer and Communication Engineering, Changsha University of Science and Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wei","family":"Wang","sequence":"additional","affiliation":[{"name":"Hunan Provincial Key Laboratory of Intelligent Processing of Big Data on Transportation & College of Computer and Communication Engineering, Changsha University of Science and Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"publisher","unstructured":"[1] U. S. Mehtaet al.: \u201cRun-length-based test data compression techniques: How far from entropy and power bounds?\u2014A survey,\u201d VLSI Design <b>2010<\/b> (2010) 670476 (DOI: 10.1155\/2010\/670476).","DOI":"10.1155\/2010\/670476"},{"key":"2","unstructured":"[2] P. T. Gonciari, <i>et al.<\/i>: \u201cImproving compression ratio, area overhead and test application time for system-on-a-chip test data compression\/decompression,\u201d Design, Automation &amp; Test in Europe Conf. (2002) 604 (DOI: 10.1109\/DATE.2002.998363)."},{"key":"3","doi-asserted-by":"publisher","unstructured":"[3] Z. Youet al.: \u201cA scan disabling-based BAST scheme for test cost reduction,\u201d IEICE Electron. Express <b>8<\/b> (2011) 1367 (DOI: 10.1587\/elex.8.1367).","DOI":"10.1587\/elex.8.1367"},{"key":"4","doi-asserted-by":"publisher","unstructured":"[4] A. Jaset al.: \u201cAn efficient test vector compression scheme using selective Huffman coding,\u201d IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. <b>22<\/b> (2003) 797 (DOI: 10.1109\/TCAD.2003.811452).","DOI":"10.1109\/TCAD.2003.811452"},{"key":"5","doi-asserted-by":"publisher","unstructured":"[5] X. Kavousianoset al.: \u201cOptimal selective Huffman coding for test-data compression,\u201d IEEE Trans. Comput. <b>56<\/b> (2007) 1146 (DOI: 10.1109\/TC.2007.1057).","DOI":"10.1109\/TC.2007.1057"},{"key":"6","doi-asserted-by":"publisher","unstructured":"[6] P. Sismanoglou and D. Nikolos: \u201cInput test data compression based on the reuse of parts of dictionary entries: Static and dynamic approaches,\u201d IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. <b>32<\/b> (2013) 1762 (DOI: 10.1109\/TCAD.2013.2270433).","DOI":"10.1109\/TCAD.2013.2270433"},{"key":"7","doi-asserted-by":"publisher","unstructured":"[7] T. B. Wuet al.: \u201cEfficient test compression technique for SOC based on block merging and eight coding,\u201d J. Electron. Test. <b>29<\/b> (2013) 849 (DOI: 10.1007\/s10836-013-5415-7).","DOI":"10.1007\/s10836-013-5415-7"},{"key":"8","doi-asserted-by":"publisher","unstructured":"[8] A. Chandra and K. Chakrabarty: \u201cSystem-on-a-chip test-data compression and decompression architectures based on Golomb codes,\u201d IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. <b>20<\/b> (2001) 355 (DOI: 10.1109\/43.913754).","DOI":"10.1109\/43.913754"},{"key":"9","doi-asserted-by":"publisher","unstructured":"[9] A. Chandra and K. Chakrabarty: \u201cTest data compression and test resource partitioning for system-on-a-chip using frequency-directed run-length (FDR) codes,\u201d IEEE Trans. Comput. <b>52<\/b> (2003) 1076 (DOI: 10.1109\/TC.2003.1223641).","DOI":"10.1109\/TC.2003.1223641"},{"key":"10","doi-asserted-by":"publisher","unstructured":"[10] P. T. Gonciariet al.: \u201cVariable-length input Huffman coding for system-on-a-chip test,\u201d IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. <b>22<\/b> (2003) 783 (DOI: 10.1109\/TCAD.2003.811451).","DOI":"10.1109\/TCAD.2003.811451"},{"key":"11","doi-asserted-by":"publisher","unstructured":"[11] A. H. El-Maleh: \u201cTest data compression for system-on-a-chip using extended frequency-directed run-length code,\u201d IET Comput. Digit. Tech. <b>2<\/b> (2008) 155 (DOI: 10.1049\/iet-cdt:20070028).","DOI":"10.1049\/iet-cdt:20070028"},{"key":"12","doi-asserted-by":"publisher","unstructured":"[12] A. Chandra and K. Chakrabarty: \u201cA unified approach to reduce SOC test data volume, scan power and testing time,\u201d IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. <b>22<\/b> (2003) 352 (DOI: 10.1109\/TCAD.2002.807895).","DOI":"10.1109\/TCAD.2002.807895"},{"key":"13","doi-asserted-by":"publisher","unstructured":"[13] M. Nourani and M. H. Tehranipour: \u201cRL-Huffman encoding for test compression and power reduction in scan application,\u201d ACM Trans. Des. Autom. Electron. Syst. <b>10<\/b> (2005) 91 (DOI: 10.1145\/1044111.1044117).","DOI":"10.1145\/1044111.1044117"},{"key":"14","doi-asserted-by":"publisher","unstructured":"[14] I. Hamzaoglu and J. H. Patel: \u201cTest set compaction algorithms for combinational circuits,\u201d IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. <b>19<\/b> (2000) 957 (DOI: 10.1109\/43.856980).","DOI":"10.1109\/43.856980"},{"key":"15","doi-asserted-by":"publisher","unstructured":"[15] H. K. Lee and D. S. Ha: \u201cHOPE: An efficient parallel fault simulator for synchronous sequential circuits,\u201d IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. <b>15<\/b> (1996) 1048 (DOI: 10.1109\/43.536711).","DOI":"10.1109\/43.536711"},{"key":"16","unstructured":"[16] R. Sankaralingam, <i>et al.<\/i>: \u201cStatic compaction techniques to control scan vector power dissipation,\u201d Proc.18th IEEE VLSI Test Symposium (2000) 35 (DOI: 10.1109\/VTEST.2000.843824)."}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/14\/13\/14_14.20170502\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,7,14]],"date-time":"2017-07-14T23:56:06Z","timestamp":1500076566000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/14\/13\/14_14.20170502\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017]]},"references-count":16,"journal-issue":{"issue":"13","published-print":{"date-parts":[[2017]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.14.20170502","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2017]]}}}