{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,13]],"date-time":"2026-05-13T16:14:15Z","timestamp":1778688855472,"version":"3.51.4"},"reference-count":13,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"13","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2017]]},"DOI":"10.1587\/elex.14.20170570","type":"journal-article","created":{"date-parts":[[2017,6,22]],"date-time":"2017-06-22T22:14:59Z","timestamp":1498169699000},"page":"20170570-20170570","source":"Crossref","is-referenced-by-count":6,"title":["Improved stacked-diode ESD protection in nanoscale CMOS technology"],"prefix":"10.1587","volume":"14","author":[{"given":"Chun-Yu","family":"Lin","sequence":"first","affiliation":[{"name":"Department of Electrical Engineering, National Taiwan Normal University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Meng-Ting","family":"Lin","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, National Taiwan Normal University"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"publisher","unstructured":"[1] I. Hwang and I. Kwon: \u201cUltra-wideband CMOS low-noise amplifier with active interferer rejection,\u201d IEICE Electron. Express <b>13<\/b> (2016) 20160597 (DOI: 10.1587\/elex.13.20160597).","DOI":"10.1587\/elex.13.20160597"},{"key":"2","doi-asserted-by":"publisher","unstructured":"[2] M. Tsaiet al.: \u201cA wideband low noise amplifier with 4 kV HBM ESD protection in 65 nm RF CMOS,\u201d IEEE Microw. Wireless Compon. Lett. <b>19<\/b> (2009) 734 (DOI: 10.1109\/LMWC.2009.2032019).","DOI":"10.1109\/LMWC.2009.2032019"},{"key":"3","doi-asserted-by":"publisher","unstructured":"[3] Y. Yanget al.: \u201cDegradation of high-k\/metal gate nMOSFETs under ESD-like stress in a 32-nm technology,\u201d IEEE Trans. Device Mater. Rel. <b>11<\/b> (2011) 118 (DOI: 10.1109\/TDMR.2010.2098407).","DOI":"10.1109\/TDMR.2010.2098407"},{"key":"4","unstructured":"[4] C. Lin, <i>et al.<\/i>: \u201cStudy on the ESD-induced gate-oxide breakdown and the protection solution in 28 nm high-k metal-gate CMOS technology,\u201d Proc. IEEE Nanotechnology Materials and Devices Conf. (2015) 63 (DOI: 10.1109\/NMDC.2015.7439250)."},{"key":"5","doi-asserted-by":"publisher","unstructured":"[5] M. Keret al.: \u201cOverview on ESD protection designs of low-parasitic capacitance for RF ICs in CMOS technologies,\u201d IEEE Trans. Device Mater. Rel. <b>11<\/b> (2011) 207 (DOI: 10.1109\/TDMR.2011.2106129).","DOI":"10.1109\/TDMR.2011.2106129"},{"key":"6","doi-asserted-by":"publisher","unstructured":"[6] C. Yehet al.: \u201cOptimization on layout style of ESD protection diode for radio-frequency front-end and high-speed I\/O interface circuits,\u201d IEEE Trans. Device Mater. Rel. <b>10<\/b> (2010) 238 (DOI: 10.1109\/TDMR.2010.2043433).","DOI":"10.1109\/TDMR.2010.2043433"},{"key":"7","doi-asserted-by":"publisher","unstructured":"[7] M. Ker: \u201cWhole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuit for submicron CMOS VLSI,\u201d IEEE Trans. Electron Devices <b>46<\/b> (1999) 173 (DOI: 10.1109\/16.737457).","DOI":"10.1109\/16.737457"},{"key":"8","unstructured":"[8] M. Ker, <i>et al.<\/i>: \u201cESD protection design for CMOS RF integrated circuits,\u201d Proc. EOS\/ESD Symp. (2001) 344."},{"key":"9","unstructured":"[9] A. Wang, <i>et al.<\/i>: \u201cESD protection design for RF integrated circuits: new challenges,\u201d Proc. IEEE Custom Integrated Circuits Conf. (2002) 411 (DOI: 10.1109\/CICC.2002.1012860)."},{"key":"10","doi-asserted-by":"publisher","unstructured":"[10] M. Ker and K. Hsu: \u201cOverview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits,\u201d IEEE Trans. Device Mater. Rel. <b>5<\/b> (2005) 235 (DOI: 10.1109\/TDMR.2005.846824).","DOI":"10.1109\/TDMR.2005.846824"},{"key":"11","doi-asserted-by":"publisher","unstructured":"[11] Y. Koo and K. Lee: \u201cSCR-based ESD protection device with low trigger and high robustness for I\/O clamp,\u201d IEICE Electron. Express <b>9<\/b> (2012) 200 (DOI: 10.1587\/elex.9.200).","DOI":"10.1587\/elex.9.200"},{"key":"12","doi-asserted-by":"publisher","unstructured":"[12] S. Janget al.: \u201cDynamic triggering characteristics of SCR-type electrostatic discharge protection circuits,\u201d Solid-State Electron. <b>45<\/b> (2001) 1091 (DOI: 10.1016\/S0038-1101(01)00142-3).","DOI":"10.1016\/S0038-1101(01)00142-3"},{"key":"13","doi-asserted-by":"publisher","unstructured":"[13] M. Mergenset al.: \u201cSpeed optimized diode-triggered SCR (DTSCR) for RF ESD protection of ultra-sensitive IC nodes in advanced technologies,\u201d IEEE Trans. Device Mater. Rel. <b>5<\/b> (2005) 532 (DOI: 10.1109\/TDMR.2005.853510).","DOI":"10.1109\/TDMR.2005.853510"}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/14\/13\/14_14.20170570\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,7,15]],"date-time":"2017-07-15T03:56:26Z","timestamp":1500090986000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/14\/13\/14_14.20170570\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017]]},"references-count":13,"journal-issue":{"issue":"13","published-print":{"date-parts":[[2017]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.14.20170570","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2017]]}}}