{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,5]],"date-time":"2022-04-05T18:41:37Z","timestamp":1649184097543},"reference-count":11,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"23","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2017]]},"DOI":"10.1587\/elex.14.20171017","type":"journal-article","created":{"date-parts":[[2017,11,20]],"date-time":"2017-11-20T22:03:54Z","timestamp":1511215434000},"page":"20171017-20171017","source":"Crossref","is-referenced-by-count":0,"title":["Design procedure of 25.8 Gbps\/lane re-timer IC regarding power integrity"],"prefix":"10.1587","volume":"14","author":[{"given":"Kenji","family":"Kogo","sequence":"first","affiliation":[{"name":"Research & Development Group, Hitachi Ltd."}]},{"given":"Takayasu","family":"Norimatsu","sequence":"additional","affiliation":[{"name":"Research & Development Group, Hitachi Ltd."}]},{"given":"Norihiro","family":"Kohmu","sequence":"additional","affiliation":[{"name":"Research & Development Group, Hitachi Ltd."}]},{"given":"Takashi","family":"Kawamoto","sequence":"additional","affiliation":[{"name":"Research & Development Group, Hitachi Ltd."}]}],"member":"532","reference":[{"key":"1","unstructured":"[1] Y. Doi, <i>et al.<\/i>: \u201cA 32 Gb\/s data-interpolator receiver with 2-tap DFE in 28 nm CMOS,\u201d ISSCC Dig. Tech. Papers (2013) 36 (DOI: 10.1109\/ISSCC.2013.6487626)."},{"key":"2","unstructured":"[2] T. Kawamoto, <i>et al.<\/i>: \u201cMulti-standard 185 fsrms 0.3-to-28 Gb\/s 40 dB backplane signal conditioner with adaptive pattern-match 36-Tap DFE and data-rate-adjustment PLL in 28 nm CMOS,\u201d ISSCC Dig. Tech. Papers (2015) 54 (DOI: 10.1109\/ISSCC.2015.7062922)."},{"key":"3","unstructured":"[3] M. Chandana, <i>et al<\/i>.: \u201cPower integrity analysis for high performance design,\u201d 2015 ICCEREC (2015) 48 (DOI: 10.1109\/ICCEREC.2015.7337052)."},{"key":"4","unstructured":"[4] K. Kogo, <i>et al.<\/i>: \u201cPower signal integrity for 25 Gbps 40 dB compensation signal conditioner for backplane architecture,\u201d 2015ICSJ (2015) 212 (DOI: 10.1109\/ICSJ.2015.7357400)."},{"key":"5","unstructured":"[5] W. Li-xin, <i>et al.<\/i>: \u201cPower integrity analysis for high-speed PCB,\u201d 2010 First International Conference on Pervasive Computing, Signal Processing and Applications (2010) 414 (DOI: 10.1109\/PCSPA.2010.106)."},{"key":"6","unstructured":"[6] B. Hassan and S. Mouloud: \u201cAnalysis and optimization of power integrity issues from high speed CMOS integrated circuit interactions in aeronautic systems,\u201d 2016 IEEE, 13th International Multi-Conference on Systems, Signals &amp; Devices (2016) 636 (DOI: 10.1109\/SSD.2016.7473674)."},{"key":"7","unstructured":"[7] R. Sjiariel, <i>et al<\/i>.: \u201cPower integrity simulation of power delivery network system,\u201d 2015 IMOC (2015) 1 (DOI: 10.1109\/IMOC.2015.7369185)."},{"key":"8","unstructured":"[8] Y. Uematsu, <i>et al<\/i>.: \u201cChip-package-PCB co-simulation for power integrity design at the early design stage,\u201d 2015 APCAP (2015) 451 (DOI: 10.1109\/APCAP.2015.7374446)."},{"key":"9","unstructured":"[9] M. J. Patil, <i>et al<\/i>.: \u201cTechniques for detection of package issues in chip power integrity closure,\u201d 2016 EPEPS (2016) 79 (DOI: 10.1109\/EPEPS.2016.7835422)."},{"key":"10","unstructured":"[10] H. Kimura, <i>et al.<\/i>: \u201c28 Gb\/s 560 mW multi-standard SerDes with single-stage analog front-end and 14-tap decision-feedback equalizer in 28 nm CMOS,\u201d ISSCC Dig. Tech. Papers (2014) 38 (DOI: 10.1109\/ISSCC.2014.6757327)."},{"key":"11","unstructured":"[11] B. Zhang, <i>et al.<\/i>: \u201cA 28 Gb\/s multi-standard serial-link transceiver for backplane applications in 28 nm CMOS,\u201d ISSCC Dig. Tech. Papers (2015) 1 (DOI: 10.1109\/ISSCC.2015.7062921)."}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/14\/23\/14_14.20171017\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,12,16]],"date-time":"2017-12-16T03:54:56Z","timestamp":1513396496000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/14\/23\/14_14.20171017\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017]]},"references-count":11,"journal-issue":{"issue":"23","published-print":{"date-parts":[[2017]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.14.20171017","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2017]]}}}