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Solid-State Circuits <b>44<\/b> (2009) 2891 (DOI: 10.1109\/JSSC.2009.2028917).","DOI":"10.1109\/JSSC.2009.2028917"},{"key":"5","doi-asserted-by":"publisher","unstructured":"[5] M. H. Nazariet al.: \u201cA 15-Gb\/s 0.5-mW\/Gbps two-tap DFE receiver with far-end crosstalk cancellation,\u201d IEEE J. Solid-State Circuits <b>47<\/b> (2012) 2420 (DOI: 10.1109\/JSSC.2012.2203870).","DOI":"10.1109\/JSSC.2012.2203870"},{"key":"6","doi-asserted-by":"publisher","unstructured":"[6] T. H. Ohet al.: \u201cA 6-Gb\/s mimo crosstalk cancellation scheme for high-speed I\/Os,\u201d IEEE J. Solid-State Circuits <b>46<\/b> (2011) 1843 (DOI: 10.1109\/JSSC.2011.2151410).","DOI":"10.1109\/JSSC.2011.2151410"},{"key":"7","doi-asserted-by":"publisher","unstructured":"[7] S.-K. Leeet al.: \u201cA 5 Gb\/s single-ended parallel receiver with adaptive crosstalk-induced jitter cancellation,\u201d IEEE J. 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