{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,3,30]],"date-time":"2022-03-30T15:39:23Z","timestamp":1648654763374},"reference-count":11,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"10","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2018]]},"DOI":"10.1587\/elex.15.20180397","type":"journal-article","created":{"date-parts":[[2018,5,8]],"date-time":"2018-05-08T18:21:36Z","timestamp":1525803696000},"page":"20180397-20180397","source":"Crossref","is-referenced-by-count":0,"title":["Multi-column parallel QC-LDPC decoder architecture for NAND flash memory"],"prefix":"10.1587","volume":"15","author":[{"given":"Wei","family":"Shen","sequence":"first","affiliation":[{"name":"School of Electrical Science and Engineering, Nanjing University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Cheng","family":"Chen","sequence":"additional","affiliation":[{"name":"Microelectronics R&D Institute, ZTE Corporation"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jin","family":"Sha","sequence":"additional","affiliation":[{"name":"Shenzhen Research Institute, Nanjing University"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"publisher","unstructured":"[1] G. Dong, <i>et al.<\/i>: \u201cUsing data postcompensation and predistortion to tolerate cell-to-cell interference in MLC NAND flash memory,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>57<\/b> (2010) 2718 (DOI: 10.1109\/TCSI.2010.2046966).","DOI":"10.1109\/TCSI.2010.2046966"},{"key":"2","unstructured":"[2] K. Kim: \u201cTechnology for sub-50 nm DRAM and NAND flash manufacturing,\u201d IEEE International Electron Devices Meeting, 2005. IEDM Technical Digest (2005) 323 (DOI: 10.1109\/IEDM.2005.1609340)."},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] J. Li, <i>et al.<\/i>: \u201cRealizing unequal error correction for NAND flash memory at minimal read latency overhead,\u201d IIEEE Trans. Circuits Syst. II, Exp. Briefs <b>61<\/b> (2014) 354 (DOI: 10.1109\/TCSII.2014.2312640).","DOI":"10.1109\/TCSII.2014.2312640"},{"key":"4","doi-asserted-by":"publisher","unstructured":"[4] R. Gallager: \u201cLow-density parity-check codes,\u201d IRE Trans. Inf. Theory <b>8<\/b> (1962) 21 (DOI: 10.1109\/TIT.1962.1057683).","DOI":"10.1109\/TIT.1962.1057683"},{"key":"5","doi-asserted-by":"publisher","unstructured":"[5] M. P. C. Fossorier, <i>et al.<\/i>: \u201cReduced complexity iterative decoding of low-density parity check codes based on belief propagation,\u201d IEEE Trans. Commun. <b>47<\/b> (1999) 673 (DOI: 10.1109\/26.768759).","DOI":"10.1109\/26.768759"},{"key":"6","doi-asserted-by":"publisher","unstructured":"[6] K. C. Ho, <i>et al.<\/i>: \u201cA 520k (18900, 17010) array dispersion LDPC decoder architectures for NAND flash memory,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>24<\/b> (2016) 1293 (DOI: 10.1109\/TVLSI.2015.2464092).","DOI":"10.1109\/TVLSI.2015.2464092"},{"key":"7","doi-asserted-by":"publisher","unstructured":"[7] H. C. Lee, <i>et al.<\/i>: \u201cOptimization techniques for the efficient implementation of high-rate layered QC-LDPC decoders,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>64<\/b> (2017) 457 (DOI: 10.1109\/TCSI.2016.2612655).","DOI":"10.1109\/TCSI.2016.2612655"},{"key":"8","doi-asserted-by":"publisher","unstructured":"[8] J. Li, <i>et al.<\/i>: \u201cAlgebraic quasi-cyclic LDPC codes: Construction, low error-floor, large girth and a reduced complexity decoding scheme,\u201d IEEE Trans. Commun. <b>62<\/b> (2014) 2626 (DOI: 10.1109\/TCOMM.2014.2339329).","DOI":"10.1109\/TCOMM.2014.2339329"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] M. R. Li, <i>et al.<\/i>: \u201cA low-complexity LDPC decoder for NAND flash applications,\u201d 2014 IEEE International Symposium on Circuits and Systems (ISCAS) (2014) 213 (DOI: 10.1109\/ISCAS.2014.6865103).","DOI":"10.1109\/ISCAS.2014.6865103"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] E. Eleftheriou and S. Olcer: \u201cLow-density parity-check codes for digital subscriber lines,\u201d IEEE Communication Letters (2002) 1752 (DOI: 10.1109\/ICC.2002.997149).","DOI":"10.1109\/ICC.2002.997149"},{"key":"11","unstructured":"[11] W. Shao, <i>et al.<\/i>: \u201cDispersed array LDPC codes and decoder architecture for NAND flash memory,\u201d IEEE Trans. Circuits Syst. II, Exp. Brief (DOI: 10.1109\/TCSII.2017.2783438)."}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/15\/10\/15_15.20180397\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,5,26]],"date-time":"2018-05-26T00:29:16Z","timestamp":1527294556000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/15\/10\/15_15.20180397\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018]]},"references-count":11,"journal-issue":{"issue":"10","published-print":{"date-parts":[[2018]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.15.20180397","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018]]}}}