{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,25]],"date-time":"2025-10-25T12:27:46Z","timestamp":1761395266999},"reference-count":12,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"13","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2018]]},"DOI":"10.1587\/elex.15.20180497","type":"journal-article","created":{"date-parts":[[2018,6,19]],"date-time":"2018-06-19T22:25:38Z","timestamp":1529447138000},"page":"20180497-20180497","source":"Crossref","is-referenced-by-count":4,"title":["A 700-MS\/s 6-bit SAR ADC with partially active reference voltage buffer"],"prefix":"10.1587","volume":"15","author":[{"given":"Long","family":"Zhao","sequence":"first","affiliation":[{"name":"Shanghai Research Institute of Microelectronics, Peking University"},{"name":"School of Electronics Engineering and Computer Science, Peking University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bao","family":"Li","sequence":"additional","affiliation":[{"name":"Shanghai Research Institute of Microelectronics, Peking University"},{"name":"School of Electronics Engineering and Computer Science, Peking University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yuhua","family":"Cheng","sequence":"additional","affiliation":[{"name":"Shanghai Research Institute of Microelectronics, Peking University"},{"name":"School of Electronics Engineering and Computer Science, Peking University"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] Y. M. Greshishchev, <i>et al.<\/i>: \u201cA 40 GS\/s 6 b ADC in 65 nm CMOS,\u201d ISSCC Dig. Tech. Papers (2010) 390 (DOI: 10.1109\/ISSCC.2010.5433972).","DOI":"10.1109\/ISSCC.2010.5433972"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] L. Kull, <i>et al.<\/i>: \u201cA 90 GS\/s 8 b 667 mW 64\u00d7 interleaved SAR ADC in 32 nm digital SOI CMOS,\u201d ISSCC Dig. Tech. Papers (2014) 378 (DOI: 10.1109\/ISSCC.2014.6757477).","DOI":"10.1109\/ISSCC.2014.6757477"},{"key":"3","doi-asserted-by":"publisher","unstructured":"[3] Y. Duan and E. Alon: \u201cA 12.8 GS\/s time-interleaved ADC with 25 GHz effective resolution bandwidth and 4.6 ENOB,\u201d IEEE J. Solid-State Circuits <b>49<\/b> (2014) 1725 (DOI: 10.1109\/JSSC.2014.2314448).","DOI":"10.1109\/JSSC.2014.2314448"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] P. Harikumar and J. J. Wikner: \u201cDesign of a reference voltage buffer for a 10-bit 50 MS\/s SAR ADC in 65 nm CMOS,\u201d IEEE International Symposium on Circuits and Systems (ISCAS) (2015) 249 (DOI: 10.1109\/ISCAS.2015.7168617).","DOI":"10.1109\/ISCAS.2015.7168617"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] F. Borghetti, <i>et al.<\/i>: \u201cA programmable 10 b up-to-6 MS\/s SAR-ADC featuring constant-FoM with on-chip reference voltage buffers,\u201d Proc. of the 32nd European Solid-State Circuits Conference (ESSCIRC) (2006) 502 (DOI: 10.1109\/ESSCIR.2006.307499).","DOI":"10.1109\/ESSCIR.2006.307499"},{"key":"6","doi-asserted-by":"publisher","unstructured":"[6] L. Kull, <i>et al.<\/i>: \u201cA 3.1 mW 8 b 1.2 GS\/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32 nm digital SOI CMOS,\u201d IEEE J. Solid-State Circuits <b>48<\/b> (2013) 3049 (DOI: 10.1109\/JSSC.2013.2279571).","DOI":"10.1109\/JSSC.2013.2279571"},{"key":"7","doi-asserted-by":"publisher","unstructured":"[7] M. Dessouky and A. Kaiser: \u201cVery low-voltage digital-audio \u0394\u03a3 modulator with 88-dB dynamic range using local switch bootstrapping,\u201d IEEE J. Solid-State Circuits <b>36<\/b> (2001) 349 (DOI: 10.1109\/4.910473).","DOI":"10.1109\/4.910473"},{"key":"8","doi-asserted-by":"publisher","unstructured":"[8] T. Jiang, <i>et al.<\/i>: \u201cA single-channel, 1.25-GS\/s, 6-bit, 6.08-mW asynchronous successive-approximation ADC with improved feedback delay in 40-nm CMOS,\u201d IEEE J. Solid-State Circuits <b>47<\/b> (2012) 2444 (DOI: 10.1109\/JSSC.2012.2204543).","DOI":"10.1109\/JSSC.2012.2204543"},{"key":"9","doi-asserted-by":"publisher","unstructured":"[9] C. Lee, <i>et al.<\/i>: \u201cA replica-driving technique for high performance SC circuits and pipelined ADC design,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>60<\/b> (2013) 557 (DOI: 10.1109\/TCSII.2013.2268432).","DOI":"10.1109\/TCSII.2013.2268432"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] D. Schinkel, <i>et al.<\/i>: \u201cA double-tail latch-type voltage sense amplifier with 18 ps setup + hold time,\u201d ISSCC Dig. Tech. Papers (2007) 315 (DOI: 10.1109\/ISSCC.2007.373420).","DOI":"10.1109\/ISSCC.2007.373420"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] D. G. Muratore, <i>et al.<\/i>: \u201cAn 8-bit 0.7-GS\/s single channel flash-SAR ADC in 65-nm CMOS technology,\u201d Proc. of the 42nd European Solid-State Circuits Conference (ESSCIRC) (2016) 424 (DOI: 10.1109\/ESSCIRC.2016.7598331).","DOI":"10.1109\/ESSCIRC.2016.7598331"},{"key":"12","doi-asserted-by":"publisher","unstructured":"[12] X. Zhu, <i>et al.<\/i>: \u201cA 6 mW 325 MS\/s 8 bit SAR ADC with background offset calibration,\u201d IEICE Electron. Express <b>14<\/b> (2017) 20170329 (DOI: 10.1587\/elex.14.20170329).","DOI":"10.1587\/elex.14.20170329"}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/15\/13\/15_15.20180497\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,7,14]],"date-time":"2018-07-14T05:07:44Z","timestamp":1531544864000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/15\/13\/15_15.20180497\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018]]},"references-count":12,"journal-issue":{"issue":"13","published-print":{"date-parts":[[2018]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.15.20180497","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018]]}}}