{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,2]],"date-time":"2022-04-02T05:34:11Z","timestamp":1648877651614},"reference-count":14,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"17","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2018]]},"DOI":"10.1587\/elex.15.20180635","type":"journal-article","created":{"date-parts":[[2018,8,23]],"date-time":"2018-08-23T18:36:01Z","timestamp":1535049361000},"page":"20180635-20180635","source":"Crossref","is-referenced-by-count":1,"title":["A high-throughput network on-chip in full-mesh architecture"],"prefix":"10.1587","volume":"15","author":[{"given":"Hongyu","family":"Meng","sequence":"first","affiliation":[{"name":"Institute of Automation, Chinese Academy of Sciences"},{"name":"University of Chinese Academy of Sciences"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lei","family":"Yang","sequence":"additional","affiliation":[{"name":"Institute of Automation, Chinese Academy of Sciences"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zijun","family":"Liu","sequence":"additional","affiliation":[{"name":"Institute of Automation, Chinese Academy of Sciences"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Donglin","family":"Wang","sequence":"additional","affiliation":[{"name":"Institute of Automation, Chinese Academy of Sciences"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"publisher","unstructured":"[1] K. Goossens, <i>et al.<\/i>: \u201cAEthereal network on chip: Concepts, architectures, and implementations,\u201d IEEE Des. Test Comput. <b>22<\/b> (2005) 414 (DOI: 10.1109\/MDT.2005.99).","DOI":"10.1109\/MDT.2005.99"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] T. Nguyen, <i>et al.<\/i>: \u201cHigh-performance adaption of ARM processors into network-on-chip architectures,\u201d IEEE International SOC Conference (2014) 222 (DOI: 10.1109\/SOCC.2013.6749691).","DOI":"10.1109\/SOCC.2013.6749691"},{"key":"3","unstructured":"[3] W. J. Dally and B. Towles: \u201cRoute packets, not wires: On-chip interconnection networks,\u201d Proc. 38th Design Automation Conference (2001) 684 (DOI: 10.1109\/DAC.2001.156225)."},{"key":"4","unstructured":"[4] B. Grot, <i>et al.<\/i>: \u201cExpress cube topologies for on-chip interconnects,\u201d 2009 IEEE 15th International Symposium on High Performance Computer Architecture (2009) 163 (DOI: 10.1109\/HPCA.2009.4798251)."},{"key":"5","unstructured":"[5] G. Chrysos: \u201cIntel<sup>\u00ae<\/sup> Xeon Phi coprocessor (codename Knights Corner),\u201d 2012 IEEE Hot Chips 24 Symposium (2012) 1 (DOI: 10.1109\/HOTCHIPS.2012.7476487)."},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] B. Bowhill, <i>et al.<\/i>: \u201cThe Xeon<sup>\u00ae<\/sup> processor E5-2600 v3: A 22 nm 18-core product family,\u201d IEEE J. Solid-State Circuits <b>51<\/b> (2016) 92 (DOI: 10.1109\/JSSC.2015.2472598).","DOI":"10.1109\/JSSC.2015.2472598"},{"key":"7","doi-asserted-by":"publisher","unstructured":"[7] A. Sodani, <i>et al.<\/i>: \u201cKnights landing: Second-generation Intel Xeon Phi product,\u201d IEEE Micro <b>36<\/b> (2016) 34 (DOI: 10.1109\/MM.2016.25).","DOI":"10.1109\/MM.2016.25"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] G. Passas, <i>et al.<\/i>: \u201cA 128 \u00d7 128 \u00d7 24 Gb\/s crossbar interconnecting 128 tiles in a single hop and occupying 6% of their area,\u201d 2010 Fourth ACM\/IEEE International Symposium on Networks-on-Chip (2010) 87 (DOI: 10.1109\/NOCS.2010.37).","DOI":"10.1109\/NOCS.2010.37"},{"key":"9","doi-asserted-by":"publisher","unstructured":"[9] C.-L. Wu and T.-Y. Feng: \u201cOn a class of multistage interconnection networks,\u201d IEEE Trans. Comput. <b>C-29<\/b> (1980) 694 (DOI: 10.1109\/TC.1980.1675651).","DOI":"10.1109\/TC.1980.1675651"},{"key":"10","unstructured":"[10] J. Balfour and W. J. Dally: \u201cDesign tradeoffs for tiled CMP on-chip networks,\u201d ACM International Conference on Supercomputing 25th Anniversary Volume (2014) 390 (DOI: 10.1145\/2591635.2667187)."},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] J. Kim, <i>et al.<\/i>: \u201cFlattened butterfly topology for on-chip networks,\u201d 40th Annual IEEE\/ACM International Symposium on Microarchitecture (2007) 172 (DOI: 10.1109\/MICRO.2007.29).","DOI":"10.1109\/MICRO.2007.29"},{"key":"12","doi-asserted-by":"publisher","unstructured":"[12] G. Passas, <i>et al.<\/i>: \u201cCrossbar NoCs are scalable beyond 100 nodes,\u201d IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. <b>31<\/b> (2012) 573 (DOI: 10.1109\/TCAD.2011.2176730).","DOI":"10.1109\/TCAD.2011.2176730"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] Y.-H. Kao, <i>et al.<\/i>: \u201cDesign of high-radix clos network-on-chip,\u201d Fourth ACM\/IEEE International Symposium on Networks-on-Chip (2010) 181 (DOI: 10.1109\/NOCS.2010.27).","DOI":"10.1109\/NOCS.2010.27"},{"key":"14","doi-asserted-by":"publisher","unstructured":"[14] M. Lin and N. McKeown: \u201cThe throughput of a buffered crossbar switch,\u201d IEEE Commun. Lett. <b>9<\/b> (2005) 465 (DOI: 10.1109\/LCOMM.2005.1431173).","DOI":"10.1109\/LCOMM.2005.1431173"}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/15\/17\/15_15.20180635\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,9,15]],"date-time":"2018-09-15T19:59:02Z","timestamp":1537041542000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/15\/17\/15_15.20180635\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018]]},"references-count":14,"journal-issue":{"issue":"17","published-print":{"date-parts":[[2018]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.15.20180635","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018]]}}}