{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,12]],"date-time":"2026-06-12T17:07:13Z","timestamp":1781284033080,"version":"3.54.1"},"reference-count":12,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"19","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2018]]},"DOI":"10.1587\/elex.15.20180753","type":"journal-article","created":{"date-parts":[[2018,9,5]],"date-time":"2018-09-05T18:24:00Z","timestamp":1536171840000},"page":"20180753-20180753","source":"Crossref","is-referenced-by-count":36,"title":["A novel self-recoverable and triple nodes upset resilience DICE latch"],"prefix":"10.1587","volume":"15","author":[{"given":"Dianpeng","family":"Lin","sequence":"first","affiliation":[{"name":"Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences"},{"name":"University of Chinese Academy of Sciences"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yiran","family":"Xu","sequence":"additional","affiliation":[{"name":"Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences"},{"name":"University of Chinese Academy of Sciences"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Xiaoyun","family":"Li","sequence":"additional","affiliation":[{"name":"Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences"},{"name":"University of Chinese Academy of Sciences"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Xin","family":"Xie","sequence":"additional","affiliation":[{"name":"Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences"},{"name":"University of Chinese Academy of Sciences"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jianwei","family":"Jiang","sequence":"additional","affiliation":[{"name":"Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences"},{"name":"University of Chinese Academy of Sciences"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jiangchuan","family":"Ren","sequence":"additional","affiliation":[{"name":"Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences"},{"name":"University of Chinese Academy of Sciences"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Huilong","family":"Zhu","sequence":"additional","affiliation":[{"name":"Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences"},{"name":"University of Chinese Academy of Sciences"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Zhengxuan","family":"Zhang","sequence":"additional","affiliation":[{"name":"Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Shichang","family":"Zou","sequence":"additional","affiliation":[{"name":"Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"publisher","unstructured":"[1] E. Ibe, <i>et al.<\/i>: \u201cImpact of scaling on neutron-induced soft error in SRAMs from a 250 nm to a 22 nm design rule,\u201d IEEE Trans. Electron Devices <b>57<\/b> (2010) 1527 (DOI: 10.1109\/TED.2010.2047907).","DOI":"10.1109\/TED.2010.2047907"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] P. E. Dodd and L. W. Massengill: \u201cBasic mechanisms and modeling of single-event upset in digital microelectronics,\u201d IEEE Trans. Nucl. Sci. <b>50<\/b> (2003) 583 (DOI: 10.1109\/TNS.2003.813129).","DOI":"10.1109\/TNS.2003.813129"},{"key":"3","doi-asserted-by":"publisher","unstructured":"[3] C. Qi, <i>et al.<\/i>: \u201cLow cost and highly reliable radiation hardened latch in 65 nm CMOS technology,\u201d Microelectron. Reliab. <b>55<\/b> (2015) 863 (DOI: 10.1016\/j.microrel.2015.03.014).","DOI":"10.1016\/j.microrel.2015.03.014"},{"key":"4","doi-asserted-by":"publisher","unstructured":"[4] M. Omana, <i>et al.<\/i>: \u201cLatch susceptibility to transient faults and new hardening approach,\u201d IEEE Trans. Comput. <b>56<\/b> (2007) 1255 (DOI: 10.1109\/TC.2007.1070).","DOI":"10.1109\/TC.2007.1070"},{"key":"5","doi-asserted-by":"publisher","unstructured":"[5] X. Hui and Z. Yun: \u201cCircuit and layout combination technique to enhance multiple nodes upset tolerance in latches,\u201d IEICE Electron. Express <b>12<\/b> (2015) 20150286 (DOI: 10.1587\/elex.12.20150286).","DOI":"10.1587\/elex.12.20150286"},{"key":"6","doi-asserted-by":"publisher","unstructured":"[6] A. Yan, <i>et al.<\/i>: \u201cA transient pulse dually filterable and online self-recoverable latch,\u201d IEICE Electron. Express <b>14<\/b> (2017) 20160911 (DOI: 10.1587\/elex.13.20160911).","DOI":"10.1587\/elex.13.20160911"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] N. Eftaxiopoulos, <i>et al.<\/i>: \u201cDelta DICE: A double node upset resilient latch,\u201d MWSCAS (2015) 1 (DOI: 10.1109\/MWSCAS.2015.7282145).","DOI":"10.1109\/MWSCAS.2015.7282145"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] N. Eftaxiopoulos, <i>et al.<\/i>: \u201cDONUT: A double node upset tolerant latch,\u201d ISVLSI (2015) 509 (DOI: 10.1109\/ISVLSI.2015.72).","DOI":"10.1109\/ISVLSI.2015.72"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] A. Watkins and S. Tragoudas: \u201cRadiation hardened latch designs for double and triple node upsets,\u201d IEEE Trans. Emerg. Top. Comput. (2017) 1 (DOI: 10.1109\/TETC.2017.2776285).","DOI":"10.1109\/TETC.2017.2776285"},{"key":"10","doi-asserted-by":"publisher","unstructured":"[10] S. Lin, <i>et al.<\/i>: \u201cAnalysis and design of nanoscale CMOS storage elements for single-event hardening with multiple-node upset,\u201d IEEE Trans. Device Mater. Rel. <b>12<\/b> (2012) 68 (DOI: 10.1109\/TDMR.2011.2167233).","DOI":"10.1109\/TDMR.2011.2167233"},{"key":"11","doi-asserted-by":"publisher","unstructured":"[11] G. C. Messenger, <i>et al.<\/i>: \u201cCollection of charge on junction nodes from ion tracks,\u201d IEEE Trans. Nucl. Sci. <b>29<\/b> (1982) 2024 (DOI: 10.1109\/TNS.1982.4336490).","DOI":"10.1109\/TNS.1982.4336490"},{"key":"12","doi-asserted-by":"publisher","unstructured":"[12] H. Nan, <i>et al.<\/i>: \u201cHigh performance, low cost, and robust soft error tolerant latch designs for nanoscale CMOS technology,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>59<\/b> (2012) 1445 (DOI: 10.1109\/TCSI.2011.2177135).","DOI":"10.1109\/TCSI.2011.2177135"}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/15\/19\/15_15.20180753\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,10,13]],"date-time":"2018-10-13T00:27:07Z","timestamp":1539390427000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/15\/19\/15_15.20180753\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018]]},"references-count":12,"journal-issue":{"issue":"19","published-print":{"date-parts":[[2018]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.15.20180753","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018]]}}}