{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,6,22]],"date-time":"2024-06-22T08:34:48Z","timestamp":1719045288115},"reference-count":14,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"4","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2019]]},"DOI":"10.1587\/elex.16.20181147","type":"journal-article","created":{"date-parts":[[2019,2,5]],"date-time":"2019-02-05T22:20:49Z","timestamp":1549405249000},"page":"20181147-20181147","source":"Crossref","is-referenced-by-count":3,"title":["A bypass-based low latency network-on-chip router"],"prefix":"10.1587","volume":"16","author":[{"given":"Peng","family":"Guo","sequence":"first","affiliation":[{"name":"Institute of Automation, Chinese Academy of Sciences"},{"name":"University of Chinese Academy of Sciences"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Qingbin","family":"Liu","sequence":"additional","affiliation":[{"name":"Institute of Automation, Chinese Academy of Sciences"},{"name":"University of Chinese Academy of Sciences"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ruizhi","family":"Chen","sequence":"additional","affiliation":[{"name":"Institute of Automation, Chinese Academy of Sciences"},{"name":"University of Chinese Academy of Sciences"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lei","family":"Yang","sequence":"additional","affiliation":[{"name":"Institute of Automation, Chinese Academy of Sciences"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Donglin","family":"Wang","sequence":"additional","affiliation":[{"name":"Institute of Automation, Chinese Academy of Sciences"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] P. Gratz, <i>et al.<\/i>: \u201cImplementation and evaluation of on-chip network architectures,\u201d ICCD (2006) 477 (DOI: 10.1109\/ICCD.2006.4380859).","DOI":"10.1109\/ICCD.2006.4380859"},{"key":"2","doi-asserted-by":"publisher","unstructured":"[2] Y. Hoskote, <i>et al.<\/i>: \u201cA 5-ghz mesh interconnect for a teraflops processor,\u201d IEEE Micro <b>27<\/b> (2007) 51 (DOI: 10.1109\/MM.2007.4378783).","DOI":"10.1109\/MM.2007.4378783"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] G. Michelogiannakis, <i>et al.<\/i>: \u201cElastic-buffer flow control for on-chip networks,\u201d HPCA (2009) 151 (DOI: 10.1109\/HPCA.2009.4798250).","DOI":"10.1109\/HPCA.2009.4798250"},{"key":"4","unstructured":"[4] D. U. Becker, <i>et al.<\/i>: \u201cEfficient microarchitecture for network-on-chip routers,\u201d Ph.D Dissertation, Stanford University (2011)."},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] R. Mullins, <i>et al.<\/i>: \u201cLow-latency virtual-channel routers for on-chip networks,\u201d ISCA (2004) 188 (DOI: 10.1109\/ISCA.2004.1310774).","DOI":"10.1109\/ISCA.2004.1310774"},{"key":"6","doi-asserted-by":"publisher","unstructured":"[6] W. J. Dally, <i>et al.<\/i>: \u201cVirtual-channel flow control,\u201d ISCA (1992) 194 (DOI: 10.1109\/71.127260).","DOI":"10.1109\/71.127260"},{"key":"7","doi-asserted-by":"publisher","unstructured":"[7] M. Galles, <i>et al.<\/i>: \u201cSpider: A high-speed network interconnect,\u201d IEEE Micro <b>17<\/b> (1997) 34 (DOI: 10.1109\/40.566196).","DOI":"10.1109\/40.566196"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] L.-S. Peh and W. J. Dally: \u201cDelay model and speculative architecture for pipelined routers,\u201d HPCA (2000) 255 (DOI: 10.1109\/HPCA.2001.903268).","DOI":"10.1109\/HPCA.2001.903268"},{"key":"9","doi-asserted-by":"publisher","unstructured":"[9] T. Moscibroda and O. Mutlu: \u201cA case for bufferless routing in on-chip networks,\u201d ACM SIGARCH (2009) 196 (DOI: 10.1145\/1555815.1555781).","DOI":"10.1145\/1555815.1555781"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] C.-K. Hsu, <i>et al.<\/i>: \u201cA low power detection routing method for bufferless noc,\u201d ISQED (2013) 364 (DOI: 10.1109\/ISQED.2013.6523636).","DOI":"10.1109\/ISQED.2013.6523636"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] Y. Lu, <i>et al.<\/i>: \u201cExploring virtual-channel architecture in FPGA based networks-on-chip,\u201d SOCC (2011) 302 (DOI: 10.1109\/SOCC.2011.6085089).","DOI":"10.1109\/SOCC.2011.6085089"},{"key":"12","doi-asserted-by":"publisher","unstructured":"[12] A. Monemi, <i>et al.<\/i>: \u201cLow latency network-on-chip router microarchitecture using request masking technique,\u201d IJRC (2015) 2 (DOI: 10.1155\/2015\/570836).","DOI":"10.1155\/2015\/570836"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] A. Kumar, <i>et al.<\/i>: \u201cExpress virtual channels: Towards the ideal interconnection fabric,\u201d ISCA (2007) 150 (DOI: 10.1145\/1250662.1250681).","DOI":"10.1145\/1250662.1250681"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] D. Wang, <i>et al.<\/i>: \u201cMaPU: A novel mathematical computing architecture,\u201d HPCA (2016) 457 (DOI: 10.1109\/HPCA.2016.7446086).","DOI":"10.1109\/HPCA.2016.7446086"}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/16\/4\/16_16.20181147\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,3,2]],"date-time":"2019-03-02T05:30:10Z","timestamp":1551504610000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/16\/4\/16_16.20181147\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019]]},"references-count":14,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2019]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.16.20181147","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019]]}}}