{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,4]],"date-time":"2025-09-04T14:35:26Z","timestamp":1756996526856},"reference-count":31,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"6","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2019]]},"DOI":"10.1587\/elex.16.20190007","type":"journal-article","created":{"date-parts":[[2019,3,7]],"date-time":"2019-03-07T22:31:20Z","timestamp":1551997880000},"page":"20190007-20190007","source":"Crossref","is-referenced-by-count":5,"title":["A 12-bit 100-MS\/s 83 dB SFDR SAR ADC with sampling switch linearity enhanced technique"],"prefix":"10.1587","volume":"16","author":[{"given":"Xu","family":"Dai-guo","sequence":"first","affiliation":[{"name":"School of Microelectronics and Solid-State Electronics, University of Electronic Science and Technology of China"},{"name":"Science and Technology on Analog Integrated Circuit Laboratory"}]},{"family":"Pu-Jie","sequence":"additional","affiliation":[{"name":"Science and Technology on Analog Integrated Circuit Laboratory"}]},{"given":"Xu","family":"Shi-liu","sequence":"additional","affiliation":[{"name":"Science and Technology on Analog Integrated Circuit Laboratory"}]},{"given":"Zhang","family":"Zheng-ping","sequence":"additional","affiliation":[{"name":"Science and Technology on Analog Integrated Circuit Laboratory"}]},{"given":"Zhang","family":"Jun-an","sequence":"additional","affiliation":[{"name":"School of Artificial Intelligengce, Chongqing University of Technology"}]},{"given":"Wang","family":"Jian-an","sequence":"additional","affiliation":[{"name":"Science and Technology on Analog Integrated Circuit Laboratory"}]}],"member":"532","reference":[{"key":"1","unstructured":"[1] C.-C. Liu, <i>et al.<\/i>: \u201cA 10b 100 MS\/s 1.13 mW SAR ADC with binary-scaled error compensation,\u201d ISSCC Dig. Tech. Papers (2010) 386 (DOI: 10.1109\/ISSCC.2010.5433970)."},{"key":"2","unstructured":"[2] J. Craninckx and G. van der Plas: \u201cA 65 fJ\/conversion-step 0-to-50 MS\/s 0-to-0.7 mW 9b charge-sharing SAR ADC in 90 nm digital CMOS,\u201d ISSCC Dig. Tech. Papers (2007) 246 (DOI: 10.1109\/ISSCC.2007.373386)."},{"key":"3","unstructured":"[3] V. Giannini, <i>et al.<\/i>: \u201cAn 820 \u00b5W 9b 40 MS\/s noise-tolerant dynamic-SAR ADC in 90 nm digital CMOS,\u201d ISSCC Dig. Tech. Papers (2008) 238 (DOI: 10.1109\/ISSCC.2008.4523145)."},{"key":"4","unstructured":"[4] H. Nakane, <i>et al.<\/i>: \u201cA fully integrated SAR ADC using digital correction technique for triple-mode mobile transceiver,\u201d ASSCC (2013) 73 (DOI: 10.1109\/ASSCC.2013.6690985)."},{"key":"5","doi-asserted-by":"publisher","unstructured":"[5] J. Fang, <i>et al.<\/i>: \u201cA 5-GS\/s 10-b 76-mW time-interleaved SAR ADC in 28 nm CMOS,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>64<\/b> (2017) 1673 (DOI: 10.1109\/TCSI.2017.2661481).","DOI":"10.1109\/TCSI.2017.2661481"},{"key":"6","doi-asserted-by":"publisher","unstructured":"[6] J. Luo, <i>et al.<\/i>: \u201cA 0.9-V 12-bit 100-MS\/s 14.6-fJ\/Conversion-Step SAR ADC in 40-nm CMOS,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>26<\/b> (2018) 1980 (DOI: 10.1109\/TVLSI.2018.2846746).","DOI":"10.1109\/TVLSI.2018.2846746"},{"key":"7","unstructured":"[7] Z. Cao, <i>et al.<\/i>: \u201cA 32 mW 1.25 GS\/s 6b 2b\/step SAR ADC in 0.13 \u00b5m CMOS,\u201d ISSCC Dig. Tech. Papers (2008) 542 (DOI: 10.1109\/ISSCC.2008.4523297)."},{"key":"8","doi-asserted-by":"publisher","unstructured":"[8] C. C. Liu, <i>et al.<\/i>: \u201cA 10-bit 50-MS\/s SAR ADC with a monotonic capacitor switching procedure,\u201d IEEE J. Solid-State Circuits <b>45<\/b> (2010) 731 (DOI: 10.1109\/JSSC.2010.2042254).","DOI":"10.1109\/JSSC.2010.2042254"},{"key":"9","doi-asserted-by":"publisher","unstructured":"[9] Y. Zhou, <i>et al.<\/i>: \u201cA 12 bit 160 MS\/s two-step SAR ADC with background bit-weight calibration using a time-domain proximity detector,\u201d IEEE J. Solid-State Circuits <b>50<\/b> (2015) 920 (DOI: 10.1109\/JSSC.2014.2384025).","DOI":"10.1109\/JSSC.2014.2384025"},{"key":"10","unstructured":"[10] K.-H. Chang and C.-C. Hsieh: \u201cA 12 bit 150 MS\/s 1.5 mW SAR ADC with adaptive radix DAC in 40 nm CMOS,\u201d ASSCC (2016) 157 (DOI: 10.1109\/ASSCC.2016.7844159)."},{"key":"11","doi-asserted-by":"publisher","unstructured":"[11] J.-H. Tsai, <i>et al.<\/i>: \u201cA 0.003 mm<sup>2<\/sup> 10b 240 MS\/s 0.7 mW SAR ADC in 28 nm CMOS with digital error correction and correlated-reversed switching,\u201d IEEE J. Solid-State Circuits <b>50<\/b> (2015) 1382 (DOI: 10.1109\/JSSC.2015.2413850).","DOI":"10.1109\/JSSC.2015.2413850"},{"key":"12","doi-asserted-by":"publisher","unstructured":"[12] W.-H. Tseng, <i>et al.<\/i>: \u201cA 12-bit 104 MS\/s SAR ADC in 28 nm CMOS for digitally-assisted wireless transmitters,\u201d IEEE J. Solid-State Circuits <b>51<\/b> (2016) 2222 (DOI: 10.1109\/JSSC.2016.2582861).","DOI":"10.1109\/JSSC.2016.2582861"},{"key":"13","doi-asserted-by":"publisher","unstructured":"[13] T.-H. Tsai, <i>et al.<\/i>: \u201cAn 8b 700 MS\/s 1b\/cycle SAR ADC using a delay-shift technique,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>63<\/b> (2016) 683 (DOI: 10.1109\/TCSI.2016.2529278).","DOI":"10.1109\/TCSI.2016.2529278"},{"key":"14","unstructured":"[14] V. Tripathi and B. Murmann: \u201cAn 8-bit 450-MS\/s single-bit\/cycle SAR ADC in 65-nm CMOS,\u201d ESSCIRC (2013) 117 (DOI: 10.1109\/ESSCIRC.2013.6649086)."},{"key":"15","doi-asserted-by":"publisher","unstructured":"[15] H. Huang, <i>et al.<\/i>: \u201cA 1.2-GS\/s 8-bit two-step SAR ADC in 65-nm CMOS with passive residue transfer,\u201d IEEE J. Solid-State Circuits <b>52<\/b> (2017) 1551 (DOI: 10.1109\/JSSC.2017.2682839).","DOI":"10.1109\/JSSC.2017.2682839"},{"key":"16","doi-asserted-by":"publisher","unstructured":"[16] S. Liu, <i>et al.<\/i>: \u201cA 12-bit 10 MS\/s SAR ADC with high linearity and energy-efficient switching,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>63<\/b> (2016) 1616 (DOI: 10.1109\/TCSI.2016.2581177).","DOI":"10.1109\/TCSI.2016.2581177"},{"key":"17","doi-asserted-by":"publisher","unstructured":"[17] X. Y. Wang, <i>et al.<\/i>: \u201cDesign considerations of ultra low-voltage self-calibrated SAR ADC,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>62<\/b> (2015) 337 (DOI: 10.1109\/TCSII.2014.2387654).","DOI":"10.1109\/TCSII.2014.2387654"},{"key":"18","doi-asserted-by":"publisher","unstructured":"[18] J. F. Gao, <i>et al.<\/i>: \u201cA monotonic SAR ADC with system-level error correction,\u201d Analog Integr. Circuits Signal Process. <b>84<\/b> (2015) 1 (DOI: 10.1007\/s10470-015-0543-x).","DOI":"10.1007\/s10470-015-0543-x"},{"key":"19","doi-asserted-by":"publisher","unstructured":"[19] C.-C. Liu, <i>et al.<\/i>: \u201cA 12 bit 100 MS\/s SAR-assisted digital-slope ADC,\u201d IEEE J. Solid-State Circuits <b>51<\/b> (2016) 2941 (DOI: 10.1109\/JSSC.2016.2591822).","DOI":"10.1109\/JSSC.2016.2591822"},{"key":"20","doi-asserted-by":"publisher","unstructured":"[20] D. Zhang, <i>et al.<\/i>: \u201cA 53-nW 9.1-ENOB 1-kS\/s SAR ADC in 0.13 \u00b5m CMOS for medical implant devices,\u201d IEEE J. Solid-State Circuits <b>47<\/b> (2012) 1585 (DOI: 10.1109\/JSSC.2012.2191209).","DOI":"10.1109\/JSSC.2012.2191209"},{"key":"21","doi-asserted-by":"publisher","unstructured":"[21] G.-Y. Huang, <i>et al.<\/i>: \u201c10-bit 30-MS\/s SAR ADC using a switchback switching method,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>21<\/b> (2013) 584 (DOI: 10.1109\/TVLSI.2012.2190117).","DOI":"10.1109\/TVLSI.2012.2190117"},{"key":"22","doi-asserted-by":"publisher","unstructured":"[22] W. Kim, <i>et al.<\/i>: \u201cA 0.6 V 12b 10 MS\/s low-noise asynchronous SAR-assisted time-interleaved SAR (SATI-SAR) ADC,\u201d IEEE J. Solid-State Circuits <b>51<\/b> (2016) 1826 (DOI: 10.1109\/JSSC.2016.2563780).","DOI":"10.1109\/JSSC.2016.2563780"},{"key":"23","unstructured":"[23] L. Kull, <i>et al.<\/i>: \u201cA 90 GS\/s 8b 667 mW 64\u00d7 interleaved SAR ADC in 32 nm digital SOI CMOS,\u201d ISSCC Dig. Tech. Papers (2014) 378 (DOI: 10.1109\/ISSCC.2014.6757477)."},{"key":"24","unstructured":"[24] B.-R.-S. Sung, <i>et al.<\/i>: \u201cA 21 fJ\/conv-step 9 ENOB 1.6 GS\/S 2\u00d7 time-interleaved FATI SAR ADC with background offset and timing skew calibration in 45 nm CMOS,\u201d ISSCC Dig. Tech. Papers (2015) 464 (DOI: 10.1109\/ISSCC.2015.7063127)."},{"key":"25","unstructured":"[25] M. Brandolini, <i>et al.<\/i>: \u201cA 5 GS\/S 150 mW 10b SHA-less pipelined\/SAR hybrid ADC in 28 nm CMOS,\u201d ISSCC Dig. Tech. Papers (2015) 468 (DOI: 10.1109\/ISSCC.2015.7063129)."},{"key":"26","doi-asserted-by":"publisher","unstructured":"[26] J.-W. Nam, <i>et al.<\/i>: \u201cA 12-bit 1.6, 3.2, and 6.4 GS\/s 4-b\/cycle time-interleaved SAR ADC with dual reference shifting and interpolation,\u201d IEEE J. Solid-State Circuits <b>53<\/b> (2018) 1765 (DOI: 10.1109\/JSSC.2018.2808244).","DOI":"10.1109\/JSSC.2018.2808244"},{"key":"27","doi-asserted-by":"publisher","unstructured":"[27] X. Dai-guo, <i>et al.<\/i>: \u201cA 10-bit 1.2 GS\/s 45 mW time-interleaved SAR ADC with background calibration,\u201d IEICE Electron. Express <b>15<\/b> (2018) 20171235 (DOI: 10.1587\/elex.15.20171235).","DOI":"10.1587\/elex.15.20171235"},{"key":"28","doi-asserted-by":"publisher","unstructured":"[28] S. Lee, <i>et al.<\/i>: \u201cA 1 GS\/s 10b 18.9 mW time-interleaved SAR ADC with background timing skew calibration,\u201d IEEE J. Solid-State Circuits <b>49<\/b> (2014) 2846 (DOI: 10.1109\/JSSC.2014.2362851).","DOI":"10.1109\/JSSC.2014.2362851"},{"key":"29","doi-asserted-by":"publisher","unstructured":"[29] W. Yang, <i>et al.<\/i>: \u201cA 3-V 340-mW 14-b 75-Msample\/s CMOS ADC with 85-dB SFDR at Nyquist input,\u201d IEEE J. Solid-State Circuits <b>36<\/b> (2001) 1931 (DOI: 10.1109\/4.972143).","DOI":"10.1109\/4.972143"},{"key":"30","unstructured":"[30] J. Brunsilius, <i>et al.<\/i>: \u201cA 16b 80 MS\/s 100 mW 77.6 dB SNR CMOS pipeline ADC,\u201d ISSCC Dig. Tech. Papers (2011) 186 (DOI: 10.1109\/ISSCC.2011.5746275)."},{"key":"31","doi-asserted-by":"publisher","unstructured":"[31] D. Xu, <i>et al.<\/i>: \u201cA linearity-improved 8-bit 320 MS\/s SAR ADC with meta-stability immunity technique,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>26<\/b> (2018) 1545 (DOI: 10.1109\/TVLSI.2018.2822678).","DOI":"10.1109\/TVLSI.2018.2822678"}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/16\/6\/16_16.20190007\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,25]],"date-time":"2019-05-25T03:22:45Z","timestamp":1558754565000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/16\/6\/16_16.20190007\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019]]},"references-count":31,"journal-issue":{"issue":"6","published-print":{"date-parts":[[2019]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.16.20190007","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019]]}}}