{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,30]],"date-time":"2025-10-30T22:39:19Z","timestamp":1761863959474},"reference-count":31,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"8","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2019]]},"DOI":"10.1587\/elex.16.20190090","type":"journal-article","created":{"date-parts":[[2019,4,3]],"date-time":"2019-04-03T22:17:39Z","timestamp":1554329859000},"page":"20190090-20190090","source":"Crossref","is-referenced-by-count":7,"title":["A low power wide tuning range two stage ring VCO with frequency enhancing"],"prefix":"10.1587","volume":"16","author":[{"given":"Chenggang","family":"Yan","sequence":"first","affiliation":[{"name":"Southeast University"}]},{"given":"Jianhui","family":"Wu","sequence":"additional","affiliation":[{"name":"Southeast University"}]},{"given":"Chen","family":"Hu","sequence":"additional","affiliation":[{"name":"Southeast University"}]},{"given":"Xincun","family":"Ji","sequence":"additional","affiliation":[{"name":"Nanjing University of Posts and Telecommunications"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"publisher","unstructured":"[1] J. Kim, <i>et al.<\/i>: \u201cA low phase noise multi-band LC VCO using a switched differential inductor,\u201d IEICE Electron. Express <b>15<\/b> (2018) 20180155 (DOI: 10.1587\/elex.15.20180155).","DOI":"10.1587\/elex.15.20180155"},{"key":"2","doi-asserted-by":"publisher","unstructured":"[2] M. Sankararaju and S. Dharmar: \u201cDesign of low power CMOS LC VCO for direct conversion transceiver,\u201d Turk. J. Electr. Eng. Comput. Sci. <b>24<\/b> (2016) 3263 (DOI: 10.3906\/elk-1407-24).","DOI":"10.3906\/elk-1407-24"},{"key":"3","unstructured":"[3] A. Molnar, <i>et al.<\/i>: \u201cA single-chip quad-band (850\/900\/1800\/1900 MHz) direct-conversion GSM\/GPRS RF transceiver with integrated VCOs and fractional-N synthesizer,\u201d 2002 IEEE International Solid-State Circuits Conference (ISSCC). Digest of Technical Papers <b>1<\/b> (2002) (DOI: 10.1109\/ISSCC.2002.993021)."},{"key":"4","doi-asserted-by":"publisher","unstructured":"[4] Y. Song, <i>et al.<\/i>: \u201cAn on-chip antenna integrated with a transceiver in 0.18-\u00b5m CMOS technology,\u201d IEICE Electron. Express <b>14<\/b> (2017) 20170836 (DOI: 10.1587\/elex.14.20170836).","DOI":"10.1587\/elex.14.20170836"},{"key":"5","doi-asserted-by":"publisher","unstructured":"[5] Y. Chai, <i>et al.<\/i>: \u201cDesign of a 60-GHz receiver front-end with broadband matching techniques in 65-nm CMOS,\u201d IEICE Electron. Express <b>15<\/b> (2018) 20180935 (DOI: 10.1587\/elex.15.20180935).","DOI":"10.1587\/elex.15.20180935"},{"key":"6","unstructured":"[6] G. Hasenaecker, <i>et al.<\/i>: \u201cA SiGe fractional-N frequency synthesizer for mm-wave wideband FMCW radar transceivers,\u201d IEEE Trans. Microw. Theory Techn. <b>64<\/b> (2016) 847 (DOI: 10.1109\/TMTT.2016.2520469)."},{"key":"7","doi-asserted-by":"publisher","unstructured":"[7] W. El-Halwagy, <i>et al.<\/i>: \u201cA 28-GHz quadrature fractional-N frequency synthesizer for 5G transceivers with less than 100-fs jitter based on cascaded PLL architecture,\u201d IEEE Trans. Microw. Theory Techn. <b>65<\/b> (2017) 396 (DOI: 10.1109\/TMTT.2016.2647698).","DOI":"10.1109\/TMTT.2016.2647698"},{"key":"8","unstructured":"[8] X. Yi, <i>et al.<\/i>: \u201cA 65 nm CMOS carrier-aggregation transceiver for IEEE 802.11 WLAN applications,\u201d 2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) (2016) 67 (DOI: 10.1109\/RFIC.2016.7508252)."},{"key":"9","doi-asserted-by":"publisher","unstructured":"[9] W. Bae, <i>et al.<\/i>: \u201cA 7.6 mW, 414 fs RMS-jitter 10 GHz phase-locked loop for a 40 Gb\/S serial link transmitter based on a two-stage ring oscillator in 65 nm CMOS,\u201d IEEE J. Solid-State Circuits <b>51<\/b> (2016) 2357 (DOI: 10.1109\/JSSC.2016.2579159).","DOI":"10.1109\/JSSC.2016.2579159"},{"key":"10","unstructured":"[10] C. Zhai, <i>et al.<\/i>: \u201cAn N-path filter enhanced low phase noise ring VCO,\u201d IEEE Symposium on VLSI Circuits Digest of Technical Papers (2014) 1 (DOI: 10.1109\/VLSIC.2014.6858448)."},{"key":"11","doi-asserted-by":"publisher","unstructured":"[11] B. Razavi: \u201cChallenges in the design high-speed clock and data recovery circuits,\u201d IEEE Commun. Mag. <b>40<\/b> (2002) 94 (DOI: 10.1109\/MCOM.2002.1024421).","DOI":"10.1109\/MCOM.2002.1024421"},{"key":"12","doi-asserted-by":"publisher","unstructured":"[12] M. Rau, <i>et al.<\/i>: \u201cClock\/data recovery PLL using half-frequency clock,\u201d IEEE J. Solid-State Circuits <b>32<\/b> (1997) 1156 (DOI: 10.1109\/4.597310).","DOI":"10.1109\/4.597310"},{"key":"13","doi-asserted-by":"publisher","unstructured":"[13] J. E. Rogers and J. R. Long: \u201cA 10-Gb\/s CDR\/DEMUX with LC delay line VCO in 0.18-\/spl mu\/m CMOS,\u201d IEEE J. Solid-State Circuits <b>37<\/b> (2002) 1781 (DOI: 10.1109\/JSSC.2002.804337).","DOI":"10.1109\/JSSC.2002.804337"},{"key":"14","unstructured":"[14] J. Lee and B. Razavi: \u201cA 40 Gb\/s clock and data recovery circuit in 0.18\/spl mu\/m CMOS technology,\u201d 2003 IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers (2003) (DOI: 10.1109\/ISSCC.2003.1234285)."},{"key":"15","doi-asserted-by":"publisher","unstructured":"[15] E. Guerrero, <i>et al.<\/i>: \u201cAn adaptive bitrate clock and data recovery circuit for communication signal analyzers,\u201d IEEE Trans. Instrum. Meas. <b>66<\/b> (2017) 191 (DOI: 10.1109\/TIM.2016.2614745).","DOI":"10.1109\/TIM.2016.2614745"},{"key":"16","doi-asserted-by":"publisher","unstructured":"[16] N. H. Tho, <i>et al.<\/i>: \u201cA 200 Mb\/s\u223c3.2 Gb\/s referenceless clock and data recovery circuit with bidirectional frequency detector,\u201d IEICE Electron. Express <b>14<\/b> (2017) 20161279 (DOI: 10.1587\/elex.14.20161279).","DOI":"10.1587\/elex.14.20161279"},{"key":"17","doi-asserted-by":"publisher","unstructured":"[17] B.-H. Choi, <i>et al.<\/i>: \u201cA burst-mode clock and data recovery circuit with two symmetric quadrature VCO\u2019s,\u201d IEICE Electron. Express <b>13<\/b> (2016) 20161086 (DOI: 10.1587\/elex.13.20161086).","DOI":"10.1587\/elex.13.20161086"},{"key":"18","unstructured":"[18] J. Yin, <i>et al.<\/i>: \u201cA 0.003 mm2 1.7-to-3.5 GHz dual-mode time-interleaved ring-VCO achieving 90-to-150 kHz 1\/f3 phase-noise corner,\u201d IEEE ISSCC (2016) 48 (DOI: 10.1109\/ISSCC.2016.7417900)."},{"key":"19","doi-asserted-by":"publisher","unstructured":"[19] C. Yan and C. Hu: \u201cA 0.65-V process variation and supply noise insensitive ring VCO,\u201d Int. J. Electron. <b>105<\/b> (2017) 337 (DOI: 10.1080\/00207217.2017.1357204).","DOI":"10.1080\/00207217.2017.1357204"},{"key":"20","doi-asserted-by":"publisher","unstructured":"[20] W.-H. Chen, <i>et al.<\/i>: \u201cA 0.5 V, 440 \u00b5W frequency synthesizer for implantable medical devices,\u201d IEEE J. Solid-State Circuits <b>47<\/b> (2012) 1896 (DOI: 10.1109\/JSSC.2012.2196315).","DOI":"10.1109\/JSSC.2012.2196315"},{"key":"21","doi-asserted-by":"publisher","unstructured":"[21] W. S. T. Yan and H. C. Luong: \u201cA 900-MHz CMOS low-phase-noise voltage-controlled ring oscillator,\u201d IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process. <b>48<\/b> (2001) 216 (DOI: 10.1109\/82.917794).","DOI":"10.1109\/82.917794"},{"key":"22","unstructured":"[22] H. Liu, <i>et al.<\/i>: \u201cA 10.3 mW 13.6 GHz phase-locked loop with boosted Gm two-stage ring VCO,\u201d 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) (2016) 1443 (DOI: 10.1109\/ICSICT.2016.7998763)."},{"key":"23","doi-asserted-by":"publisher","unstructured":"[23] J. Lee, <i>et al.<\/i>: \u201cLinearly frequency-tunable and low-phase noise ring VCO using varactors with optimally spaced bias voltages,\u201d Electron. Lett. <b>54<\/b> (2018) 342 (DOI: 10.1049\/el.2017.4394).","DOI":"10.1049\/el.2017.4394"},{"key":"24","doi-asserted-by":"publisher","unstructured":"[24] X. Ji, <i>et al.<\/i>: \u201cA linearized tuning varactor for voltage controlled oscillator,\u201d IEICE Electron. Express <b>14<\/b> (2017) 20170730 (DOI: 10.1587\/elex.14.20170730).","DOI":"10.1587\/elex.14.20170730"},{"key":"25","doi-asserted-by":"publisher","unstructured":"[25] H. J. Choi, <i>et al.<\/i>: \u201cSub-1 V VI converter-based voltage-controlled oscillator with a linear gain characteristic,\u201d IEICE Electron. Express <b>14<\/b> (2017) 20170610 (DOI: 10.1587\/elex.14.20170610).","DOI":"10.1587\/elex.14.20170610"},{"key":"26","unstructured":"[26] K. Chen, <i>et al.<\/i>: \u201cA wide tuning range ring VCO with low phase noise in 90 nm CMOS,\u201d IEEE Conference on Electron Devices and Solid-State Circuits (2014) (DOI: 10.1109\/EDSSC.2014.7061153)."},{"key":"27","unstructured":"[27] N. Retdian, <i>et al.<\/i>: \u201cVoltage controlled ring oscillator with wide tuning range and fast voltage swing,\u201d Proc. IEEE Asia-Pacific Conference on ASIC (2002) 201 (DOI: 10.1109\/APASIC.2002.1031567)."},{"key":"28","doi-asserted-by":"publisher","unstructured":"[28] A. Elkholy, <i>et al.<\/i>: \u201cA 2.0\u20135.5 GHz wide bandwidth ring-based digital fractional-N PLL with extended range multi-modulus divider,\u201d IEEE J. Solid-State Circuits <b>51<\/b> (2016) 1771 (DOI: 10.1109\/JSSC.2016.2557807).","DOI":"10.1109\/JSSC.2016.2557807"},{"key":"29","doi-asserted-by":"publisher","unstructured":"[29] A. Hajimiri, <i>et al.<\/i>: \u201cJitter and phase noise in ring oscillators,\u201d IEEE J. Solid-State Circuits <b>34<\/b> (1999) 790 (DOI: 10.1109\/4.766813).","DOI":"10.1109\/4.766813"},{"key":"30","doi-asserted-by":"publisher","unstructured":"[30] Z. Changchun, <i>et al.<\/i>: \u201cA CMOS high-performance inductorless ring VCO with extended monotonic tuning voltage range,\u201d IEICE Electron. Express <b>15<\/b> (2018) 20180941 (DOI: 10.1587\/elex.15.20180941).","DOI":"10.1587\/elex.15.20180941"},{"key":"31","unstructured":"[31] K. R. Lakshmikumar, <i>et al.<\/i>: \u201cA process and temperature compensated two-stage ring oscillator,\u201d IEEE CICC (2007) 691 (DOI: 10.1109\/CICC.2007.4405826)."}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/16\/8\/16_16.20190090\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,4,27]],"date-time":"2019-04-27T03:33:34Z","timestamp":1556336014000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/16\/8\/16_16.20190090\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019]]},"references-count":31,"journal-issue":{"issue":"8","published-print":{"date-parts":[[2019]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.16.20190090","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019]]}}}