{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,1]],"date-time":"2026-06-01T12:36:06Z","timestamp":1780317366543,"version":"3.54.1"},"reference-count":30,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"11","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2019]]},"DOI":"10.1587\/elex.16.20190208","type":"journal-article","created":{"date-parts":[[2019,5,12]],"date-time":"2019-05-12T18:03:05Z","timestamp":1557684185000},"page":"20190208-20190208","source":"Crossref","is-referenced-by-count":6,"title":["A single event upset tolerant latch with parallel nodes"],"prefix":"10.1587","volume":"16","author":[{"given":"Changyong","family":"Liu","sequence":"first","affiliation":[{"name":"School of Electronics and Information Engineering, Anhui University"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Nianlong","family":"Liu","sequence":"additional","affiliation":[{"name":"Water Resources Information Center of Henan"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Zhiting","family":"Lin","sequence":"additional","affiliation":[{"name":"School of Electronics and Information Engineering, Anhui University"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Xiulong","family":"Wu","sequence":"additional","affiliation":[{"name":"School of Electronics and Information Engineering, Anhui University"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Chunyu","family":"Peng","sequence":"additional","affiliation":[{"name":"School of Electronics and Information Engineering, Anhui University"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Qiang","family":"Zhao","sequence":"additional","affiliation":[{"name":"School of Electronics and Information Engineering, Anhui University"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Xuan","family":"Li","sequence":"additional","affiliation":[{"name":"School of Electronics and Information Engineering, Anhui University"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Junning","family":"Chen","sequence":"additional","affiliation":[{"name":"School of Electronics and Information Engineering, Anhui University"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Xuan","family":"Zeng","sequence":"additional","affiliation":[{"name":"State Key Laboratory of ASIC & System, Department of Microelectronics, Fudan University"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Xiangdong","family":"Hu","sequence":"additional","affiliation":[{"name":"Shanghai High Performance Integrated Circuit Design Center"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"publisher","unstructured":"[1] M. Glorieux, <i>et al.<\/i>: \u201cDetailed SET measurement and characterization of a 65 nm bulk technology,\u201d IEEE Trans. Nucl. Sci. <b>64<\/b> (2017) 81 (DOI: 10.1109\/TNS.2016.2637935).","DOI":"10.1109\/TNS.2016.2637935"},{"key":"2","doi-asserted-by":"publisher","unstructured":"[2] R. Baumann: \u201cSoft errors in advanced semiconductor devices-part I: The three radiation sources,\u201d IEEE Trans. Device Mater. Rel. <b>1<\/b> (2001) 17 (DOI: 10.1109\/7298.946456).","DOI":"10.1109\/7298.946456"},{"key":"3","doi-asserted-by":"publisher","unstructured":"[3] P. E. Dodd, <i>et al.<\/i>: \u201cCurrent and future challenges in radiation effects on CMOS electronics,\u201d IEEE Trans. Nucl. Sci. <b>57<\/b> (2010) 1747 (DOI: 10.1109\/TNS.2010.2042613).","DOI":"10.1109\/TNS.2010.2042613"},{"key":"4","doi-asserted-by":"publisher","unstructured":"[4] R. Baumann: \u201cSoft errors in advanced computer systems,\u201d IEEE Des. Test Comput. <b>22<\/b> (2005) 258 (DOI: 10.1109\/MDT.2005.69).","DOI":"10.1109\/MDT.2005.69"},{"key":"5","doi-asserted-by":"publisher","unstructured":"[5] N. Seifert, <i>et al.<\/i>: \u201cImpact of scaling on soft-error rates in commercial microprocessors,\u201d IEEE Trans. Nucl. Sci. <b>49<\/b> (2002) 3100 (DOI: 10.1109\/TNS.2002.805402).","DOI":"10.1109\/TNS.2002.805402"},{"key":"6","doi-asserted-by":"publisher","unstructured":"[6] A. Yan, <i>et al.<\/i>: \u201cA double-node-upset self-recoverable latch design for high performance and low power application,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>66<\/b> (2019) 287 (DOI: 10.1109\/TCSII.2018.2849028).","DOI":"10.1109\/TCSII.2018.2849028"},{"key":"7","doi-asserted-by":"publisher","unstructured":"[7] A. K. Pudi N S and M. S. Baghini: \u201cRobust soft error tolerant CMOS latch configurations,\u201d IEEE Trans. Comput. <b>65<\/b> (2016) 2820 (DOI: 10.1109\/TC.2015.2509983).","DOI":"10.1109\/TC.2015.2509983"},{"key":"8","unstructured":"[8] P. E. Dodd, <i>et al.<\/i>: \u201cBasic mechanisms and modeling of single-event upset in digital microelectronics,\u201d IEEE Trans. Nucl. Sci. <b>50<\/b> (2003) 583 (DOI: 10.1109\/TNS.2003.813129)."},{"key":"9","doi-asserted-by":"publisher","unstructured":"[9] C. Peng, <i>et al.<\/i>: \u201cA radiation harden enhanced Quatro (RHEQ) SRAM cell,\u201d IEICE Electron. Express <b>14<\/b> (2017) 20170784 (DOI: 10.1587\/elex.14.20170784).","DOI":"10.1587\/elex.14.20170784"},{"key":"10","doi-asserted-by":"publisher","unstructured":"[10] D. Lin, <i>et al.<\/i>: \u201cA novel self-recoverable and triple nodes upset resilience DICE latch,\u201d IEICE Electron. Express <b>15<\/b> (2018) 20180753 (DOI: 10.1587\/elex.15.20180753).","DOI":"10.1587\/elex.15.20180753"},{"key":"11","doi-asserted-by":"publisher","unstructured":"[11] D. Lin, <i>et al.<\/i>: \u201cA novel highly reliable and low-power radiation hardened SRAM bit-cell design,\u201d IEICE Electron. Express <b>15<\/b> (2018) 20171129 (DOI: 10.1587\/elex.15.20171129).","DOI":"10.1587\/elex.15.20171129"},{"key":"12","doi-asserted-by":"publisher","unstructured":"[12] M. Moghaddam, <i>et al.<\/i>: \u201cDesign and evaluation of an efficient Schmitt trigger-based hardened latch in CNTFET technology,\u201d IEEE Trans. Device Mater. Rel. <b>17<\/b> (2017) 267 (DOI: 10.1109\/TDMR.2017.2665780).","DOI":"10.1109\/TDMR.2017.2665780"},{"key":"13","doi-asserted-by":"publisher","unstructured":"[13] D. Lin, <i>et al.<\/i>: \u201cA novel SEU tolerant memory cell for space applications,\u201d IEICE Electron. Express <b>15<\/b> (2018) 20180656 (DOI: 10.1587\/elex.15.20180656).","DOI":"10.1587\/elex.15.20180656"},{"key":"14","doi-asserted-by":"publisher","unstructured":"[14] X. Hui and Z. Yun: \u201cCircuit and layout combination technique to enhance multiple nodes upset tolerance in latches,\u201d IEICE Electron. Express <b>12<\/b> (2015) 20150286 (DOI: 10.1587\/elex.12.20150286).","DOI":"10.1587\/elex.12.20150286"},{"key":"15","doi-asserted-by":"publisher","unstructured":"[15] A. O. Balbekov, <i>et al.<\/i>: \u201cCircuit-level layout-aware modeling of single-event effects in 65-nm CMOS ICs,\u201d IEEE Trans. Nucl. Sci. <b>65<\/b> (2018) 1914 (DOI: 10.1109\/TNS.2018.2802205).","DOI":"10.1109\/TNS.2018.2802205"},{"key":"16","doi-asserted-by":"publisher","unstructured":"[16] H. B. Wang, <i>et al.<\/i>: \u201cAn area efficient stacked latch design tolerant to SEU in 28 nm FDSOI technology,\u201d IEEE Trans. Nucl. Sci. <b>63<\/b> (2016) 3003 (DOI: 10.1109\/TNS.2016.2627003).","DOI":"10.1109\/TNS.2016.2627003"},{"key":"17","doi-asserted-by":"publisher","unstructured":"[17] S. Lin, <i>et al.<\/i>: \u201cDesign and performance evaluation of radiation hardened latches for nanoscale CMOS,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>19<\/b> (2011) 1315 (DOI: 10.1109\/TVLSI.2010.2047954).","DOI":"10.1109\/TVLSI.2010.2047954"},{"key":"18","doi-asserted-by":"publisher","unstructured":"[18] S. Xuan, <i>et al.<\/i>: \u201cSEU hardened flip-flop based on dynamic logic,\u201d IEEE Trans. Nucl. Sci. <b>60<\/b> (2013) 3932 (DOI: 10.1109\/TNS.2013.2281138).","DOI":"10.1109\/TNS.2013.2281138"},{"key":"19","doi-asserted-by":"publisher","unstructured":"[19] K. P. Rodbell, <i>et al.<\/i>: \u201c32 and 45 nm radiation-hardened-by-design (RHBD) SOI latches,\u201d IEEE Trans. Nucl. Sci. <b>58<\/b> (2011) 2702 (DOI: 10.1109\/TNS.2011.2171715).","DOI":"10.1109\/TNS.2011.2171715"},{"key":"20","doi-asserted-by":"publisher","unstructured":"[20] J. Chen, <i>et al.<\/i>: \u201cSimulation study of the layout technique for P-hit single-event transient mitigation via the source isolation,\u201d IEEE Trans. Device Mater. Rel. <b>12<\/b> (2012) 501 (DOI: 10.1109\/TDMR.2012.2191971).","DOI":"10.1109\/TDMR.2012.2191971"},{"key":"21","doi-asserted-by":"publisher","unstructured":"[21] C. Y. Liu, <i>et al.<\/i>: \u201cA dual-output hardening design of inverter chain for P-hit single-event transient pulse elimination,\u201d IEICE Electron. Express <b>15<\/b> (2018) 20180604 (DOI: 10.1587\/elex.15.20180604).","DOI":"10.1587\/elex.15.20180604"},{"key":"22","doi-asserted-by":"publisher","unstructured":"[22] C. Y. Liu, <i>et al.<\/i>: \u201cAn inverter chain with parallel output nodes for eliminating single-event transient pulse,\u201d IEICE Electron. Express <b>16<\/b> (2019) 20181118 (DOI: 10.1587\/elex.16.20181118).","DOI":"10.1587\/elex.16.20181118"},{"key":"23","doi-asserted-by":"publisher","unstructured":"[23] A. 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Kelin, <i>et al.<\/i>: \u201cLEAP: Layout design through error-aware transistor positioning for soft-error resilient sequential cell design,\u201d Proc. IEEE IRPS (2010) 203 (DOI: 10.1109\/IRPS.2010.5488829)."},{"key":"27","doi-asserted-by":"publisher","unstructured":"[27] J. Chen, <i>et al.<\/i>: \u201cNovel layout technique for single-event transient mitigation using dummy transistor,\u201d IEEE Trans. Device Mater. Rel. <b>13<\/b> (2013) 177 (DOI: 10.1109\/TDMR.2012.2227261).","DOI":"10.1109\/TDMR.2012.2227261"},{"key":"28","unstructured":"[28] J. R. Ahlbin, <i>et al.<\/i>: \u201cDouble-pulse-single-event transients in combinational logic,\u201d Proc. IEEE IRPS (2011) 258 (DOI: 10.1109\/IRPS.2011.5784486)."},{"key":"29","doi-asserted-by":"publisher","unstructured":"[29] J. R. Ahlbin, <i>et al.<\/i>: \u201cEffect of multiple-transistor charge collection on single-event transient pulse widths,\u201d IEEE Trans. Device Mater. Rel. <b>11<\/b> (2011) 401 (DOI: 10.1109\/TDMR.2011.2157506).","DOI":"10.1109\/TDMR.2011.2157506"},{"key":"30","unstructured":"[30] S. Jagannathan, <i>et al.<\/i>: \u201cIndependent measurement of SET pulse widths from N-hits and P-hits in 65-nm CMOS,\u201d IEEE Trans. Nucl. Sci. <b>57<\/b> (2010) 3386 (DOI: 10.1109\/TNS.2010.2076836)."}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/16\/11\/16_16.20190208\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,6,14]],"date-time":"2019-06-14T23:26:08Z","timestamp":1560554768000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/16\/11\/16_16.20190208\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019]]},"references-count":30,"journal-issue":{"issue":"11","published-print":{"date-parts":[[2019]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.16.20190208","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019]]}}}