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Atzori, <i>et al.<\/i>: \u201cThe internet of things: A survey,\u201d Comput. Netw. <b>54<\/b> (2010) 2787 (DOI: 10.1016\/j.comnet.2010.05.010).","DOI":"10.1016\/j.comnet.2010.05.010"},{"key":"2","doi-asserted-by":"publisher","unstructured":"[2] J. Gubbi, <i>et al.<\/i>: \u201cInternet of things (IoT): A vision, architectural elements, and future directions,\u201d Future Gener. Comput. Syst. <b>29<\/b> (2013) 1645 (DOI: 10.1016\/j.future.2013.01.010).","DOI":"10.1016\/j.future.2013.01.010"},{"key":"3","doi-asserted-by":"publisher","unstructured":"[3] G. Lallement, <i>et al.<\/i>: \u201cA 2.7 pJ\/cycle 16 MHz, 0.7 uW deep sleep power ARM cortex-M0+ core SoC in 28 nm FD-SOI,\u201d IEEE J. Solid-State Circuits <b>53<\/b> (2018) 2088 (DOI: 10.1109\/JSSC.2018.2821167).","DOI":"10.1109\/JSSC.2018.2821167"},{"key":"4","doi-asserted-by":"publisher","unstructured":"[4] J. Li, <i>et al.<\/i>: \u201cAn area-efficient microprocessor-based SoC with an instruction-cache transformable to an ambient temperature sensor and a physically unclonable function,\u201d IEEE J. Solid-State Circuits <b>53<\/b> (2018) 728 (DOI: 10.1109\/JSSC.2018.2791460).","DOI":"10.1109\/JSSC.2018.2791460"},{"key":"5","unstructured":"[5] L. Lin, <i>et al.<\/i>: \u201cA 595 pW 14 pJ\/cycle microcontroller with dual-mode standard cells and self-startup for battery-indifferent distributed sensing,\u201d 2018 IEEE International Solid - State Circuits Conference - (ISSCC) (2018) 44 (DOI: 10.1109\/ISSCC.2018.8310175)."},{"key":"6","doi-asserted-by":"publisher","unstructured":"[6] Y. Zhang, <i>et al.<\/i>: \u201ciRazor: Current-based error detection and correction scheme for PVT variation in 40-nm ARM cortex-R4 processor,\u201d IEEE J. Solid-State Circuits <b>53<\/b> (2018) 619 (DOI: 10.1109\/JSSC.2017.2749423).","DOI":"10.1109\/JSSC.2017.2749423"},{"key":"7","doi-asserted-by":"publisher","unstructured":"[7] A. P. Chandrakasan, <i>et al.<\/i>: \u201cLow-power CMOS digital design,\u201d IEEE J. Solid-State Circuits <b>27<\/b> (1992) 473 (DOI: 10.1109\/4.126534).","DOI":"10.1109\/4.126534"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] J. Rabaey: <i>Low Power Design Essentials<\/i> (Springer Science &amp; Business Media, 2009).","DOI":"10.1007\/978-0-387-71713-5"},{"key":"9","doi-asserted-by":"publisher","unstructured":"[9] D. Bull, <i>et al.<\/i>: \u201cA power-efficient 32 bit ARM processor using timing-error detection and correction for transient-error tolerance and adaptation to PVT variation,\u201d IEEE J. Solid-State Circuits <b>46<\/b> (2011) 18 (DOI: 10.1109\/JSSC.2010.2079410).","DOI":"10.1109\/JSSC.2010.2079410"},{"key":"10","unstructured":"[10] S. Rangan, <i>et al.<\/i>: \u201cUniversal recovery behavior of negative bias temperature instability [PMOSFETs],\u201d IEEE International Electron Devices Meeting 2003 (2003) 14.3.1 (DOI: 10.1109\/IEDM.2003.1269294)."},{"key":"11","doi-asserted-by":"publisher","unstructured":"[11] A. M. Yassine, <i>et al.<\/i>: \u201cTime dependent breakdown of ultrathin gate oxide,\u201d IEEE Trans. Electron Devices <b>47<\/b> (2000) 1416 (DOI: 10.1109\/16.848285).","DOI":"10.1109\/16.848285"},{"key":"12","unstructured":"[12] N. James, <i>et al.<\/i>: \u201cComparison of split-versus connected-core supplies in the POWER6 microprocessor,\u201d 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (2007) 298 (DOI: 10.1109\/ISSCC.2007.373412)."},{"key":"13","doi-asserted-by":"publisher","unstructured":"[13] R. McGowen, <i>et al.<\/i>: \u201cPower and temperature control on a 90-nm itanium family processor,\u201d IEEE J. Solid-State Circuits <b>41<\/b> (2006) 229 (DOI: 10.1109\/JSSC.2005.859902).","DOI":"10.1109\/JSSC.2005.859902"},{"key":"14","doi-asserted-by":"publisher","unstructured":"[14] K. A. Bowman, <i>et al.<\/i>: \u201cEnergy-efficient and metastability-immune resilient circuits for dynamic variation tolerance,\u201d IEEE J. Solid-State Circuits <b>44<\/b> (2009) 49 (DOI: 10.1109\/JSSC.2008.2007148).","DOI":"10.1109\/JSSC.2008.2007148"},{"key":"15","unstructured":"[15] K. Bowman, <i>et al.<\/i>: \u201cCircuit techniques for dynamic variation tolerance,\u201d Proc. of the 46th Annual Design Automation Conference on ZZZ - DAC \u201909 (2009) 4 (DOI: 10.1145\/1629911.1629915)."},{"key":"16","doi-asserted-by":"publisher","unstructured":"[16] T. Fischer, <i>et al.<\/i>: \u201cA 90-nm variable frequency clock system for a power-managed itanium architecture processor,\u201d IEEE J. Solid-State Circuits <b>41<\/b> (2006) 218 (DOI: 10.1109\/JSSC.2005.859879).","DOI":"10.1109\/JSSC.2005.859879"},{"key":"17","unstructured":"[17] J. Tschanz, <i>et al.<\/i>: \u201cAdaptive frequency and biasing techniques for tolerance to dynamic temperature-voltage variations and aging,\u201d 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (2007) 292 (DOI: 10.1109\/ISSCC.2007.373409)."},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] C. R. Lefurgy, <i>et al.<\/i>: \u201cActive management of timing guardband to save energy in POWER7,\u201d 2011 44th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO) (2011) 1.","DOI":"10.1145\/2155620.2155622"},{"key":"19","unstructured":"[19] A. Grenat, <i>et al.<\/i>: \u201c5.6 adaptive clocking system for improved power efficiency in a 28 nm x86-64 microprocessor,\u201d 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) (2014) 106 (DOI: 10.1109\/ISSCC.2014.6757358)."},{"key":"20","unstructured":"[20] M. S. Floyd, <i>et al.<\/i>: \u201c26.5 adaptive clocking in the POWER9<sup>TM<\/sup> processor for voltage droop protection,\u201d 2017 IEEE International Solid-State Circuits Conference (ISSCC) (2017) 444 (DOI: 10.1109\/ISSCC.2017.7870452)."},{"key":"21","doi-asserted-by":"publisher","unstructured":"[21] K. A. Bowman: \u201cAdaptive and resilient circuits: A tutorial on improving processor performance, energy efficiency, and yield via dynamic variation,\u201d IEEE Solid State Circuits Mag. <b>10<\/b> (2018) 16 (DOI: 10.1109\/MSSC.2018.2844601).","DOI":"10.1109\/MSSC.2018.2844601"},{"key":"22","unstructured":"[22] J. Tschanz, <i>et al.<\/i>: \u201cA 45 nm resilient and adaptive microprocessor core for dynamic variation tolerance,\u201d 2010 IEEE International Solid-State Circuits Conference - (ISSCC) (2010) 282 (DOI: 10.1109\/ISSCC.2010.5433922)."},{"key":"23","doi-asserted-by":"publisher","unstructured":"[23] I. Kwon, <i>et al.<\/i>: \u201cRazor-lite: A light-weight register for error detection by observing virtual supply rails,\u201d IEEE J. Solid-State Circuits <b>49<\/b> (2014) 2054 (DOI: 10.1109\/JSSC.2014.2328658).","DOI":"10.1109\/JSSC.2014.2328658"},{"key":"24","doi-asserted-by":"publisher","unstructured":"[24] K. Chae and S. Mukhopadhyay: \u201cA dynamic timing error prevention technique in pipelines with time borrowing and clock stretching,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>61<\/b> (2014) 74 (DOI: 10.1109\/TCSI.2013.2268272).","DOI":"10.1109\/TCSI.2013.2268272"},{"key":"25","doi-asserted-by":"publisher","unstructured":"[25] S. Kim and M. Seok: \u201cVariation-tolerant, ultra-low-voltage microprocessor with a low-overhead, within-a-cycle in-situ timing-error detection and correction technique,\u201d IEEE J. Solid-State Circuits <b>50<\/b> (2015) 1478 (DOI: 10.1109\/JSSC.2015.2418713).","DOI":"10.1109\/JSSC.2015.2418713"},{"key":"26","unstructured":"[26] D. Ernst, <i>et al.<\/i>: \u201cRazor: A low-power pipeline based on circuit-level timing speculation,\u201d 22nd Digital Avionics Systems Conference. Proc. (Cat. No.03CH37449) (2003) 7 (DOI: 10.1109\/MICRO.2003.1253179)."},{"key":"27","doi-asserted-by":"publisher","unstructured":"[27] Y. Yu, <i>et al.<\/i>: \u201cA practical, low-overhead, one-cycle correction design method for variation-tolerant digital circuits,\u201d IEICE Electron. Express <b>15<\/b> (2018) 20171202 (DOI: 10.1587\/elex.14.20171202).","DOI":"10.1587\/elex.14.20171202"},{"key":"28","doi-asserted-by":"crossref","unstructured":"[28] A. P. Chandrakasan, <i>et al.<\/i>: <i>Design of High-Performance Microprocessor Circuits<\/i> (Wiley, IEEE Press, 2000) 1st ed.","DOI":"10.1109\/9780470544365"},{"key":"29","doi-asserted-by":"publisher","unstructured":"[29] S. Das, <i>et al.<\/i>: \u201cRazorII: In situ error detection and correction for PVT and SER tolerance,\u201d IEEE J. Solid-State Circuits <b>44<\/b> (2009) 32 (DOI: 10.1109\/JSSC.2008.2007145).","DOI":"10.1109\/JSSC.2008.2007145"},{"key":"30","unstructured":"[30] D. Hand, <i>et al.<\/i>: \u201cBlade \u2013 A timing violation resilient asynchronous template,\u201d 2015 21st IEEE International Symposium on Asynchronous Circuits and Systems (2015) 21 (DOI: 10.1109\/ASYNC.2015.13)."}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/16\/14\/16_16.20190342\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,7,27]],"date-time":"2019-07-27T03:26:49Z","timestamp":1564198009000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/16\/14\/16_16.20190342\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019]]},"references-count":30,"journal-issue":{"issue":"14","published-print":{"date-parts":[[2019]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.16.20190342","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019]]}}}