{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,28]],"date-time":"2026-02-28T14:32:19Z","timestamp":1772289139063,"version":"3.50.1"},"reference-count":30,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"15","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2019]]},"DOI":"10.1587\/elex.16.20190352","type":"journal-article","created":{"date-parts":[[2019,7,11]],"date-time":"2019-07-11T22:03:56Z","timestamp":1562882636000},"page":"20190352-20190352","source":"Crossref","is-referenced-by-count":7,"title":["An efficient background timing skew calibration technique for time-interleaving analog-to-digital converters"],"prefix":"10.1587","volume":"16","author":[{"given":"Yu","family":"Cao","sequence":"first","affiliation":[{"name":"Dept. of Information Science and Engineering, Southeast University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Peng","family":"Miao","sequence":"additional","affiliation":[{"name":"Dept. of Information Science and Engineering, Southeast University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Fei","family":"Li","sequence":"additional","affiliation":[{"name":"Dept. of Information Science and Engineering, Southeast University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Huan","family":"Wang","sequence":"additional","affiliation":[{"name":"Dept. of Information Science and Engineering, Southeast University"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"publisher","unstructured":"[1] W. C. Black and D. A. Hodges: \u201cTime-interleaved converter arrays,\u201d IEEE J. Solid-State Circuits <b>15<\/b> (1980) 1022 (DOI: 10.1109\/JSSC.1980.1051512).","DOI":"10.1109\/JSSC.1980.1051512"},{"key":"2","doi-asserted-by":"publisher","unstructured":"[2] H. Jin and E. K. F. Lee: \u201cA digital-background calibration technique for minimizing timing-error effects in time-interleaved ADCs,\u201d IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process. <b>47<\/b> (2000) 603 (DOI: 10.1109\/82.850419).","DOI":"10.1109\/82.850419"},{"key":"3","unstructured":"[3] J. Chu and H.-S. Lee: \u201cA 450 MS\/s 10-bit time-interleaved zero-crossing based ADC,\u201d IEEE Custom Integr. Circuits Conf. <b>47<\/b> (2011) 1 (DOI: 10.1109\/CICC.2011.6055327)."},{"key":"4","doi-asserted-by":"publisher","unstructured":"[4] T. Miki, <i>et al.<\/i>: \u201cA 2-GS\/s 8-bit time-interleaved SAR ADC for millimeter-wave pulsed radar baseband SoC,\u201d IEEE J. Solid-State Circuits <b>52<\/b> (2017) 2712 (DOI: 10.1109\/JSSC.2017.2732732).","DOI":"10.1109\/JSSC.2017.2732732"},{"key":"5","doi-asserted-by":"publisher","unstructured":"[5] J. W. Nam, <i>et al.<\/i>: \u201cA 12-Bit 1.6, 3.2, and 6.4 GS\/s 4-b\/cycle time-interleaved SAR ADC with dual reference shifting and interpolation,\u201d IEEE J. Solid-State Circuits <b>53<\/b> (2018) 1765 (DOI: 10.1109\/JSSC.2018.2808244).","DOI":"10.1109\/JSSC.2018.2808244"},{"key":"6","doi-asserted-by":"publisher","unstructured":"[6] S. M. Jamal, <i>et al.<\/i>: \u201cA 10-b 120-Msample\/s time-interleaved analog-to-digital converter with digital background calibration,\u201d IEEE J. Solid-State Circuits <b>37<\/b> (2002) 1618 (DOI: 10.1109\/JSSC.2002.804327).","DOI":"10.1109\/JSSC.2002.804327"},{"key":"7","doi-asserted-by":"publisher","unstructured":"[7] H. Le Duc, <i>et al.<\/i>: \u201cFully digital feedforward background calibration of clock skews for sub-sampling TIADCs using the polyphase decomposition,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>64<\/b> (2017) 1515 (DOI: 10.1109\/TCSI.2016.2645978).","DOI":"10.1109\/TCSI.2016.2645978"},{"key":"8","unstructured":"[8] M. Straayer, <i>et al.<\/i>: \u201cA 4 GS\/s time-interleaved RF ADC in 65 nm CMOS with 4 GHz input bandwidth,\u201d ISSCC Dig. Tech. Papers (2016) 464 (DOI: 10.1109\/ISSCC.2016.7418108)."},{"key":"9","doi-asserted-by":"publisher","unstructured":"[9] S. Chen, <i>et al.<\/i>: \u201cAll-digital calibration of timing mismatch error in time-interleaved analog-to-digital converters,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>25<\/b> (2017) 2552 (DOI: 10.1109\/TVLSI.2017.2703141).","DOI":"10.1109\/TVLSI.2017.2703141"},{"key":"10","unstructured":"[10] S. Liu, <i>et al.<\/i>: \u201cAll-digital background calibration technique of the channel-time-mismatch in a two-channel TIADC,\u201d IEEE Int. Conf. ASIC (2017) 632 (DOI: 10.1109\/ASICON.2017.8252555)."},{"key":"11","doi-asserted-by":"publisher","unstructured":"[11] S. Liu, <i>et al.<\/i>: \u201cAdaptive semiblind background calibration of timing mismatches in a two-channel time-interleaved analog-to-digital converter,\u201d Analog Integr. Circ. Sig. Process. <b>90<\/b> (2017) 1 (DOI: 10.1007\/s10470-016-0839-5).","DOI":"10.1007\/s10470-016-0839-5"},{"key":"12","unstructured":"[12] R. Xiao, <i>et al.<\/i>: \u201cA sinusoidal reference signal based high accuracy timing skew mismatch estimation scheme for time interleaved ADC,\u201d 17th Int. Symp. Commun. Inform. Technol. (2017) 1 (DOI: 10.1109\/ISCIT.2017.8261195)."},{"key":"13","unstructured":"[13] J. Elbornsson and J.-E. Eklund: \u201cBlind estimation of timing errors in interleaved AD converters,\u201d IEEE Int. Conf. Acoust. Speech Signal Process. <b>6<\/b> (2001) 3913 (DOI: 10.1109\/ICASSP.2001.940699)."},{"key":"14","doi-asserted-by":"publisher","unstructured":"[14] J. Elbornsson, <i>et al.<\/i>: \u201cBlind adaptive equalization of mismatch errors in a time-interleaved A\/D converter system,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>51<\/b> (2004) 151 (DOI: 10.1109\/TCSI.2003.821300).","DOI":"10.1109\/TCSI.2003.821300"},{"key":"15","unstructured":"[15] V. Divi and G. Wornell: \u201cScalable blind calibration of timing skew in high-resolution time-interleaved ADCs,\u201d IEEE Int. Symp. Circ. Syst. (2006) 3390 (DOI: 10.1109\/ISCAS.2006.1693353)."},{"key":"16","doi-asserted-by":"publisher","unstructured":"[16] S. Huang and B. C. Levy: \u201cAdaptive blind calibration of timing offset and gain mismatch for two-channel time-interleaved ADCs,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>53<\/b> (2006) 1278 (DOI: 10.1109\/TCSI.2006.875180).","DOI":"10.1109\/TCSI.2006.875180"},{"key":"17","unstructured":"[17] M. Seo, <i>et al.<\/i>: \u201cBlind correction of gain and timing mismatches for a two-channel time-interleaved analog-to-digital converter: Experimental verification,\u201d IEEE Int. Symp. Circ. Syst. (2006) 3394 (DOI: 10.1109\/ISCAS.2006.1693354)."},{"key":"18","doi-asserted-by":"publisher","unstructured":"[18] V. Divi and G. W. Wornell: \u201cBlind calibration of timing skew in time-interleaved analog-to-digital converters,\u201d IEEE J. Sel. Topics Signal Process. <b>3<\/b> (2009) 509 (DOI: 10.1109\/JSTSP.2009.2020269).","DOI":"10.1109\/JSTSP.2009.2020269"},{"key":"19","unstructured":"[19] J. Fan, <i>et al.<\/i>: \u201cBlind adaptive calibration of timing error for two-channel time-interleaved ADCs,\u201d IEEE Int. Midwest Symp. Circ. Syst. <b>3<\/b> (2010) 233 (DOI: 10.1109\/MWSCAS.2010.5548668)."},{"key":"20","doi-asserted-by":"publisher","unstructured":"[20] K. Doris, <i>et al.<\/i>: \u201cA 480 mW 2.6 GS\/s 10 b time-interleaved ADC with 48.5 dB SNDR up to Nyquist in 65 nm,\u201d IEEE J. Solid-State Circuits <b>46<\/b> (2011) 2821 (DOI: 10.1109\/JSSC.2011.2164961).","DOI":"10.1109\/JSSC.2011.2164961"},{"key":"21","doi-asserted-by":"publisher","unstructured":"[21] A. Bonnetat, <i>et al.<\/i>: \u201cAn adaptive all digital blind compensation of dual TIADC frequency-response mismatch based on complex signal correlations,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>62<\/b> (2015) 821 (DOI: 10.1109\/TCSII.2015.2435611).","DOI":"10.1109\/TCSII.2015.2435611"},{"key":"22","doi-asserted-by":"publisher","unstructured":"[22] X. Liu, <i>et al.<\/i>: \u201cAn efficient blind calibration method for nonlinearity mis-matches in M-channel TIADCs,\u201d IEICE Electron. Express <b>14<\/b> (2017) 20170468 (DOI: 10.1587\/elex.14.20170468).","DOI":"10.1587\/elex.14.20170468"},{"key":"23","doi-asserted-by":"publisher","unstructured":"[23] Y. Qiu, <i>et al.<\/i>: \u201cAll-digital blind background calibration technique for any channel time-interleaved ADC,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>65<\/b> (2018) 2503 (DOI: 10.1109\/TCSI.2018.2794529).","DOI":"10.1109\/TCSI.2018.2794529"},{"key":"24","doi-asserted-by":"publisher","unstructured":"[24] Y. Wang, <i>et al.<\/i>: \u201cBandwidth-efficient calibration method for nonlinear errors in M-channel time-interleaved ADCs,\u201d Analog Integr. Circuits Signal Process. <b>86<\/b> (2016) 275 (DOI: 10.1007\/s10470-015-0677-x).","DOI":"10.1007\/s10470-015-0677-x"},{"key":"25","doi-asserted-by":"publisher","unstructured":"[25] Y. Wang, <i>et al.<\/i>: \u201cJoint blind calibration for mixed mismatches in two-channel time-interleaved ADCs,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>62<\/b> (2015) 1508 (DOI: 10.1109\/TCSI.2015.2418835).","DOI":"10.1109\/TCSI.2015.2418835"},{"key":"26","doi-asserted-by":"crossref","unstructured":"[26] C. Chen and J. Wu: \u201cA 12 b 3 GS\/s pipeline ADC with 500 mW and 0.4 mm<sup>2<\/sup> in 40 nm digital CMOS,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>62<\/b> (2011) 120.","DOI":"10.1109\/JSSC.2012.2185192"},{"key":"27","doi-asserted-by":"publisher","unstructured":"[27] M. El-Chammas and B. Murmann: \u201cA 12-GS\/s 81-mW 5-bit time-interleaved flash ADC with background timing skew calibration,\u201d IEEE J. Solid-State Circuits <b>46<\/b> (2011) 838 (DOI: 10.1109\/JSSC.2011.2108125).","DOI":"10.1109\/JSSC.2011.2108125"},{"key":"28","doi-asserted-by":"publisher","unstructured":"[28] B. Razavi: \u201cDesign considerations for interleaved ADCs,\u201d IEEE J. Solid-State Circuits <b>48<\/b> (2013) 1806 (DOI: 10.1109\/JSSC.2013.2258814).","DOI":"10.1109\/JSSC.2013.2258814"},{"key":"29","unstructured":"[29] A. Leuciuc: \u201cSampling time calibration method for multi-channel interleaved ADCs,\u201d IEEE Int. Symp. Circ. Syst. (2017) 1 (DOI: 10.1109\/ISCAS.2017.8050247)."},{"key":"30","doi-asserted-by":"publisher","unstructured":"[30] C.-Y. Lin, <i>et al.<\/i>: \u201cA 10-bit 2.6-GS\/s time-interleaved SAR ADC with a digital-mixing timing-skew calibration technique,\u201d IEEE J. Solid-State Circuits <b>53<\/b> (2018) 1508 (DOI: 10.1109\/JSSC.2018.2793535).","DOI":"10.1109\/JSSC.2018.2793535"}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/16\/15\/16_16.20190352\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,9,23]],"date-time":"2022-09-23T18:31:28Z","timestamp":1663957888000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/16\/15\/16_16.20190352\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019]]},"references-count":30,"journal-issue":{"issue":"15","published-print":{"date-parts":[[2019]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.16.20190352","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019]]}}}