{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,7]],"date-time":"2025-11-07T13:32:31Z","timestamp":1762522351210},"reference-count":30,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"21","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2019]]},"DOI":"10.1587\/elex.16.20190544","type":"journal-article","created":{"date-parts":[[2019,10,2]],"date-time":"2019-10-02T18:04:00Z","timestamp":1570039440000},"page":"20190544-20190544","source":"Crossref","is-referenced-by-count":2,"title":["Single event upset failure probability evaluation and periodic scrubbing techniques for hierarchical parallel vision processors"],"prefix":"10.1587","volume":"16","author":[{"given":"Qian","family":"Di","sequence":"first","affiliation":[{"name":"State Key Laboratory of Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy of Sciences"},{"name":"Center of Materials Science and Optoelectronics Engineering, University of Chinese Academy of Sciences"}]},{"given":"Zhongxing","family":"Zhang","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy of Sciences"},{"name":"Center of Materials Science and Optoelectronics Engineering, University of Chinese Academy of Sciences"}]},{"given":"Honglong","family":"Li","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy of Sciences"},{"name":"Center of Materials Science and Optoelectronics Engineering, University of Chinese Academy of Sciences"}]},{"given":"Zhao","family":"Zhang","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy of Sciences"},{"name":"Center of Materials Science and Optoelectronics Engineering, University of Chinese Academy of Sciences"}]},{"given":"Peng","family":"Feng","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy of Sciences"},{"name":"Center of Materials Science and Optoelectronics Engineering, University of Chinese Academy of Sciences"}]},{"given":"Nanjian","family":"Wu","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy of Sciences"},{"name":"Center of Materials Science and Optoelectronics Engineering, University of Chinese Academy of Sciences"},{"name":"Center for Excellence in Brain Science and Intelligence Technology, Chinese Academy of Sciences"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"publisher","unstructured":"[1] W. Miao, <i>et al.<\/i>: \u201cA programmable SIMD vision chip for real-time vision applications,\u201d IEEE J. Solid-State Circuits <b>43<\/b> (2008) 1470 (DOI: 10.1109\/JSSC.2008.923621).","DOI":"10.1109\/JSSC.2008.923621"},{"key":"2","unstructured":"[2] Q. Lin, <i>et al.<\/i>: \u201cA 1,000 frames\/s programmable vision chip with variable resolution and row-pixel-mixed parallel image processors,\u201d Sensors <b>9<\/b> (2009) 5933 (DOI: 10.3390\/s90805933)."},{"key":"3","doi-asserted-by":"publisher","unstructured":"[3] W. Zhang, <i>et al.<\/i>: \u201cA programmable vision chip based on multiple levels of parallel processors,\u201d IEEE J. Solid-State Circuits <b>46<\/b> (2011) 2132 (DOI: 10.1109\/JSSC.2011.2158024).","DOI":"10.1109\/JSSC.2011.2158024"},{"key":"4","doi-asserted-by":"publisher","unstructured":"[4] C. Shi, <i>et al.<\/i>: \u201cA 1000 fps vision chip based on a dynamically reconfigurable hybrid architecture comprising a PE array processor and self-organizing map neural network,\u201d IEEE J. Solid-State Circuits <b>49<\/b> (2014) 2067 (DOI: 10.1109\/JSSC.2014.2332134).","DOI":"10.1109\/JSSC.2014.2332134"},{"key":"5","doi-asserted-by":"publisher","unstructured":"[5] J. Yang, <i>et al.<\/i>: \u201cA heterogeneous parallel processor for high-speed vision chip,\u201d IEEE Trans. Circuits Syst. Video Technol. <b>28<\/b> (2018) 746 (DOI: 10.1109\/TCSVT.2016.2618753).","DOI":"10.1109\/TCSVT.2016.2618753"},{"key":"6","unstructured":"[6] N. Wu: \u201cNeuromorphic vision chips,\u201d Sci. China Inf. Sci. <b>61<\/b> (2018) 060421 (DOI: 10.1007\/s11432-017-9303-0)."},{"key":"7","unstructured":"[7] M. Strube, <i>et al.<\/i>: <i>Raven: An On-orbit Relative Navigation Demonstration Using International Space Station Visiting Vehicles<\/i> (2015)."},{"key":"8","doi-asserted-by":"publisher","unstructured":"[8] A. Lindoso, <i>et al.<\/i>: \u201cEvaluation of the suitability of NEON SIMD microprocessor extensions under proton irradiation,\u201d IEEE Trans. Nucl. Sci. <b>65<\/b> (2018) 1835 (DOI: 10.1109\/TNS.2018.2823540).","DOI":"10.1109\/TNS.2018.2823540"},{"key":"9","unstructured":"[9] W. A. Powell, <i>et al.<\/i>: \u201cHigh-performance spaceflight computing (HPSC) project overview,\u201d Radiation Hardened Electronics Technology Conference (2018)."},{"key":"10","doi-asserted-by":"publisher","unstructured":"[10] V. Vargas, <i>et al.<\/i>: \u201cRadiation experiments on a 28 nm single-chip many-core processor and SEU error-rate prediction,\u201d IEEE Trans. Nucl. Sci. <b>64<\/b> (2017) 483 (DOI: 10.1109\/TNS.2016.2638081).","DOI":"10.1109\/TNS.2016.2638081"},{"key":"11","doi-asserted-by":"publisher","unstructured":"[11] V. Vargas, <i>et al.<\/i>: \u201cNMR-MPar: A fault-tolerance approach for multi-core and many-core processors,\u201d IEEE Trans. Nucl. Sci. <b>8<\/b> (2018) 465 (DOI: 10.3390\/app8030465).","DOI":"10.3390\/app8030465"},{"key":"12","doi-asserted-by":"publisher","unstructured":"[12] P. Ramos, <i>et al.<\/i>: \u201cSEE error-rate evaluation of an application implemented in COTS multicore\/many-core processors,\u201d IEEE Trans. Nucl. Sci. <b>65<\/b> (2018) 1879 (DOI: 10.1109\/TNS.2018.2838526).","DOI":"10.1109\/TNS.2018.2838526"},{"key":"13","doi-asserted-by":"publisher","unstructured":"[13] M. Alderighi, <i>et al.<\/i>: \u201cExperimental validation of fault injection analyses by the FLIPPER tool,\u201d IEEE Trans. Nucl. Sci. <b>57<\/b> (2010) 2129 (DOI: 10.1109\/TNS.2010.2043855).","DOI":"10.1109\/TNS.2010.2043855"},{"key":"14","doi-asserted-by":"publisher","unstructured":"[14] L. A. Naviner, <i>et al.<\/i>: \u201cFIFA: A fault-injection-fault-analysis-based tool for reliability assessment at RTL level,\u201d Microelectron. Reliab. <b>51<\/b> (2011) 1459 (DOI: 10.1016\/j.microrel.2011.06.017).","DOI":"10.1016\/j.microrel.2011.06.017"},{"key":"15","doi-asserted-by":"publisher","unstructured":"[15] W. Mansour, <i>et al.<\/i>: \u201cAn automated SEU fault-injection method and tool for HDL-based designs,\u201d IEEE Trans. Nucl. Sci. <b>60<\/b> (2013) 2728 (DOI: 10.1109\/TNS.2013.2267097).","DOI":"10.1109\/TNS.2013.2267097"},{"key":"16","doi-asserted-by":"publisher","unstructured":"[16] R. Velazco, <i>et al.<\/i>: \u201cPredicting error rate for microprocessor-based digital architectures through CEU (Code Emulating Upsets) injection,\u201d IEEE Trans. Nucl. Sci. <b>47<\/b> (2000) 2405 (DOI: 10.1109\/23.903784).","DOI":"10.1109\/23.903784"},{"key":"17","unstructured":"[17] D. Costa: <i>Fault Injection Techniques and Tools for Embedded Systems Reliability Evaluation<\/i> (Springer, 2003) 125."},{"key":"18","unstructured":"[18] E. Jenn, <i>et al.<\/i>: \u201cFault injection into VHDL models: The MEFISTO tool,\u201d International Symposium on Fault Tolerant Computing (1994) 329 (DOI: 10.1109\/FTCS.1994.315656)."},{"key":"19","unstructured":"[19] H. R. Zarandi, <i>et al.<\/i>: \u201cDependability analysis using a fault injection tool based on synthesizability of HDL models,\u201d International Symposium on Defect and Fault-Tolerance in VLSI Systems (2003) 485 (DOI: 10.1109\/DFTVS.2003.1250147)."},{"key":"20","unstructured":"[20] A. Rohani and H. G. Kerkhoff: \u201cA technique for accelerating injection of transient faults in complex SoCs,\u201d 14th Euromicro Conference on Digital System Designs (2011) 213 (DOI: 10.1109\/DSD.2011.31)."},{"key":"21","doi-asserted-by":"publisher","unstructured":"[21] A. M. Keller, <i>et al.<\/i>: \u201cBenefits of complementary SEU mitigation for the LEON3 soft processor on SRAM-based FPGAs,\u201d IEEE Trans. Nucl. Sci. <b>64<\/b> (2017) 519 (DOI: 10.1109\/TNS.2016.2635028).","DOI":"10.1109\/TNS.2016.2635028"},{"key":"22","unstructured":"[22] Z. M. Wang, <i>et al.<\/i>: \u201cThe reliability and availability analysis of SEU mitigation techniques in SRAM-based FPGAs,\u201d Radiation and Its Effects on Components and Systems (2009) 497 (DOI: 10.1109\/RADECS.2009.5994702)."},{"key":"23","doi-asserted-by":"publisher","unstructured":"[23] P. S. Ostler, <i>et al.<\/i>: \u201cSRAM FPGA reliability analysis for harsh radiation environments,\u201d IEEE Trans. Nucl. Sci. <b>56<\/b> (2009) 3519 (DOI: 10.1109\/TNS.2009.2033381).","DOI":"10.1109\/TNS.2009.2033381"},{"key":"24","unstructured":"[24] D. Patterson: <i>Computer Organization and Design: The Hardware\/Software Interface<\/i> (Elsevier, 2013) 5th ed."},{"key":"25","doi-asserted-by":"publisher","unstructured":"[25] T. Ojala, <i>et al.<\/i>: \u201cMultiresolution gray-scale and rotation invariant texture classification with local binary patterns,\u201d IEEE Trans. Pattern Anal. Mach. Intell. <b>24<\/b> (2002) 971 (DOI: 10.1109\/TPAMI.2002.1017623).","DOI":"10.1109\/TPAMI.2002.1017623"},{"key":"26","unstructured":"[26] R. Rojas, <i>et al.<\/i>: \u201cAdaboost and the Super Bowl of Classifiers a Tutorial Introduction to Adaptive Boosting,\u201d Tech. Rep (Berlin, 2009)."},{"key":"27","doi-asserted-by":"publisher","unstructured":"[27] E. Rosten, <i>et al.<\/i>: \u201cFaster and better: A machine learning approach to corner detection,\u201d IEEE Trans. Pattern Anal. Mach. Intell. <b>32<\/b> (2010) 105 (DOI: 10.1109\/TPAMI.2008.275).","DOI":"10.1109\/TPAMI.2008.275"},{"key":"28","doi-asserted-by":"publisher","unstructured":"[28] S. Luetkemeier, <i>et al.<\/i>: \u201cImagenet classification with deep convolutional neural networks,\u201d Adv. Neural Inf. Process. Syst. <b>65<\/b> (2012) 1097 (DOI: 10.1145\/3065386).","DOI":"10.1145\/3065386"},{"key":"29","doi-asserted-by":"publisher","unstructured":"[29] J. S. Browning, <i>et al.<\/i>: \u201cSingle event upset rate estimates for a 16-K CMOS SRAM,\u201d IEEE Trans. Nucl. Sci. <b>32<\/b> (1985) 4133 (DOI: 10.1109\/TNS.1985.4334081).","DOI":"10.1109\/TNS.1985.4334081"},{"key":"30","unstructured":"[30] Cogenda: ForeCAST https:\/\/forecast.cogenda.com.cn."}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/16\/21\/16_16.20190544\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,11,15]],"date-time":"2019-11-15T22:24:21Z","timestamp":1573856661000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/16\/21\/16_16.20190544\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019]]},"references-count":30,"journal-issue":{"issue":"21","published-print":{"date-parts":[[2019]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.16.20190544","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019]]}}}