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Fundamentals <b>E96-A<\/b> (2013) 453 (DOI: 10.1587\/transfun.E96.A.453).","DOI":"10.1587\/transfun.E96.A.453"},{"key":"5","unstructured":"[5] W.-Y. Pang, <i>et al.<\/i>: \u201cA 10-bit 500-KS\/s low power SAR ADC with splitting comparator for bio-medical applications,\u201d IEEE Asian Solid-State Circuits Conference (2009) 149 (DOI: 10.1109\/ASSCC.2009.5357200)."},{"key":"6","unstructured":"[6] F. Kuttner: \u201cA 1.2 V 10 b 20 MSample\/s non-binary successive approximation ADC in 0.13 \u00b5m CMOS,\u201d IEEE International Solid-State Circuits Conference Dig. Tech. Papers (2002) (DOI: 10.1109\/ISSCC.2002.992993)."},{"key":"7","doi-asserted-by":"publisher","unstructured":"[7] C.-C. Liu: \u201cA 10-bit 50-MS\/s SAR ADC with a monotonic capacitor switching procedure,\u201d IEEE J. Solid-State Circuits <b>45<\/b> (2010) 731 (DOI: 10.1109\/JSSC.2010.2042254).","DOI":"10.1109\/JSSC.2010.2042254"},{"key":"8","doi-asserted-by":"publisher","unstructured":"[8] Y. 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I, Reg. Papers <b>65<\/b> (2018) 51 (DOI: 10.1109\/TCSI.2017.2720629).","DOI":"10.1109\/TCSI.2017.2720629"},{"key":"22","doi-asserted-by":"publisher","unstructured":"[22] D. Li, <i>et al.<\/i>: \u201c1.4-mW 10-bit 150-MS\/s SAR ADC with nonbinary split capacitive DAC in 65 nm CMOS,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>65<\/b> (2018) 1524 (DOI: 10.1109\/TCSII.2017.2756036).","DOI":"10.1109\/TCSII.2017.2756036"},{"key":"23","doi-asserted-by":"publisher","unstructured":"[23] S.-M. Park, <i>et al.<\/i>: \u201cA 10-bit 20-MS\/s asynchronous SAR ADC with meta-stability detector using replica comparators,\u201d IEICE Trans. Electron. <b>E99-C<\/b> (2016) 651 (DOI: 10.1587\/transele.E99.C.651).","DOI":"10.1587\/transele.E99.C.651"},{"key":"24","doi-asserted-by":"publisher","unstructured":"[24] C. C. Lee and M. P. Flynn: \u201cA SAR-assisted two-stage pipeline ADC,\u201d IEEE J. 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Solid-State Circuits <b>54<\/b> (2019) 1648 (DOI: 10.1109\/JSSC.2019.2894998).","DOI":"10.1109\/JSSC.2019.2894998"},{"key":"28","unstructured":"[28] S. Lan, <i>et al.<\/i>: \u201cAn ultra low-power rail-to-rail comparator for ADC designs,\u201d IEEE International Midwest Symp. Circuits and Systems (2011) (DOI: 10.1109\/MWSCAS.2011.6026511)."},{"key":"29","doi-asserted-by":"publisher","unstructured":"[29] R. K. Hester, <i>et al.<\/i>: \u201cFully differential ADC with rail-to-rail common-mode range and nonlinear capacitor compensation,\u201d IEEE J. Solid-State Circuits <b>25<\/b> (1990) 173 (DOI: 10.1109\/4.50301).","DOI":"10.1109\/4.50301"},{"key":"30","unstructured":"[30] S.-M. Chin, <i>et al.<\/i>: \u201cA new rail-to-rail comparator with adaptive power control for low power SAR ADCs in biomedical application,\u201d IEEE International Symp. Circuits and Systems (2010) 1575 (DOI: 10.1109\/ISCAS.2010.5537421)."},{"key":"31","doi-asserted-by":"publisher","unstructured":"[31] S. B. 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