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S. Cannon, <i>et al.<\/i>: U.S. Patent App. 15\/809,081 (2019)."},{"key":"2","unstructured":"[2] J. R. Booth, <i>et al.<\/i>: U.S. Patent 9,929,864 (2018)."},{"key":"3","unstructured":"[3] J. S. Kim, <i>et al.<\/i>: \u201cThe dram latency puf: Quickly evaluating physical unclonable functions by exploiting the latency-reliability tradeoff in modern commodity dram devices,\u201d 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA) (2018) 194 (DOI: 10.1109\/HPCA.2018.00026)."},{"key":"4","unstructured":"[4] R. Maes, <i>et al.<\/i>: \u201cPufky: A fully functional puf-based cryptographic key generator,\u201d International Workshop on Cryptographic Hardware and Embedded Systems (2012) 302 (DOI: 10.1007\/978-3-642-33027-8_18)."},{"key":"5","unstructured":"[5] T. Ziola, <i>et al.<\/i>: U.S. Patent 8,782,396 (2014)."},{"key":"6","doi-asserted-by":"publisher","unstructured":"[6] P. Tuyls and L. Batina: \u201cRfid-tags for anti-counterfeiting,\u201d Cryptographers\u2019 Track at the RSA Conference (2006) 115 (DOI: 10.1007\/11605805_8).","DOI":"10.1007\/11605805_8"},{"key":"7","unstructured":"[7] J. Guajardo, <i>et al.<\/i>: \u201cPhysical unclonable functions and public-key crypto for fpga ip protection,\u201d 2007 International Conference on Field Programmable Logic and Applications (2007) 189 (DOI: 10.1109\/FPL.2007.4380646)."},{"key":"8","unstructured":"[8] P. Ravinkanth: \u201cPhysical one-way functions,\u201d Ph.D Thesis, MIT (2001)."},{"key":"9","unstructured":"[9] U. R\u00fchrmair and D. E. Holcomb: \u201cPufs at a glance,\u201d Proc. of the Conference on Design, Automation &amp; Test in Europe. European Design and Automation Association (2014) 347 (DOI: 10.7873\/DATE.2014.360)."},{"key":"10","unstructured":"[10] J. W. Lee, <i>et al.<\/i>: \u201cA technique to build a secret key in integrated circuits for identification and authentication applications,\u201d 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No. 04CH37525) (2004) 176 (DOI: 10.1109\/VLSIC.2004.1346548)."},{"key":"11","doi-asserted-by":"publisher","unstructured":"[11] D. Lim, <i>et al.<\/i>: \u201cExtracting secret keys from integrated circuits,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>13<\/b> (2005) 1200 (DOI: 10.1109\/TVLSI.2005.859470).","DOI":"10.1109\/TVLSI.2005.859470"},{"key":"12","doi-asserted-by":"publisher","unstructured":"[12] U. R\u00fchrmair, <i>et al.<\/i>: \u201cPuf modeling attacks on simulated and silicon data,\u201d IEEE Trans. Inf. Forensics Security <b>8<\/b> (2013) 1876 (DOI: 10.1109\/TIFS.2013.2279798).","DOI":"10.1109\/TIFS.2013.2279798"},{"key":"13","unstructured":"[13] U. R\u00fchrmair, <i>et al.<\/i>: \u201cModeling attacks on physical unclonable functions,\u201d Proc. of the 17th ACM conference on Computer and Communications Security (2010) 237 (DOI: 10.1145\/1866307.1866335)."},{"key":"14","unstructured":"[14] A. Vijayakumar, <i>et al.<\/i>: \u201cMachine learning resistant strong puf: Possible or a pipe dream?\u201d 2016 IEEE international symposium on hardware oriented security and trust (HOST) (2016) 19 (DOI: 10.1109\/HST.2016.7495550)."},{"key":"15","unstructured":"[15] J. Delvaux and I. Verbauwhede: \u201cSide channel modeling attacks on 65 nm arbiter pufs exploiting cmos device noise,\u201d 2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) (2013) 137 (DOI: 10.1109\/HST.2013.6581579)."},{"key":"16","doi-asserted-by":"publisher","unstructured":"[16] J. Delvaux and I. Verbauwhede: \u201cFault injection modeling attacks on 65 nm arbiter and ro sum pufs via environmental changes,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>61<\/b> (2014) 1701 (DOI: 10.1109\/TCSI.2013.2290845).","DOI":"10.1109\/TCSI.2013.2290845"},{"key":"17","unstructured":"[17] A. Mahmoud, <i>et al.<\/i>: \u201cCombined modeling and side channel attacks on strong pufs,\u201d IACR Cryptology ePrint Archive 2013:632 (2013)."},{"key":"18","unstructured":"[18] J. Ye, <i>et al.<\/i>: \u201cVpuf: Voter based physical unclonable function with high reliability and modeling attack resistance,\u201d 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS) (2017) 74 (DOI: 10.1109\/IOLTS.2017.8046200)."},{"key":"19","unstructured":"[19] X. Xu and W. Burleson: \u201cHybrid side-channel\/machine-learning attacks on pufs: A new threat?,\u201d Proc. of the Conference on Design, Automation &amp; Test in Europe. European Design and Automation Association (2014) 349 (DOI: 10.7873\/DATE.2014.362)."},{"key":"20","doi-asserted-by":"publisher","unstructured":"[20] B. Gassend, <i>et al.<\/i>: \u201cIdentification and authentication of integrated circuits,\u201d Concurrency Computat.: Pract. Exper. <b>16<\/b> (2004) 1077 (DOI: 10.1002\/cpe.805).","DOI":"10.1002\/cpe.805"},{"key":"21","unstructured":"[21] Q. Ma, <i>et al.<\/i>: \u201cA machine learning attack resistant multi-puf design on fpga,\u201d 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC) (2018) 97 (DOI: 10.1109\/ASPDAC.2018.8297289)."},{"key":"22","unstructured":"[22] S. S. Zalivaka, <i>et al.<\/i>: \u201cLow-cost fortification of arbiter puf against modeling attack,\u201d 2017 IEEE International Symposium on Circuits and Systems (ISCAS) (2017) 1 (DOI: 10.1109\/ISCAS.2017.8050671)."},{"key":"23","unstructured":"[23] S. S. Zalivaka, <i>et al.<\/i>: \u201cFpga implementation of modeling attack resistant arbiter puf with enhanced reliability,\u201d 2017 18th International Symposium on Quality Electronic Design (ISQED) (2017) 313 (DOI: 10.1109\/ISQED.2017.7918334)."},{"key":"24","unstructured":"[24] S. Morozov, <i>et al.<\/i>: \u201cAn analysis of delay based puf implementations on fpga,\u201d International Symposium on Applied Reconfigurable Computing (2010) 382 (DOI: 10.1007\/978-3-642-12133-3_37)."},{"key":"25","doi-asserted-by":"publisher","unstructured":"[25] H. Martin, <i>et al.<\/i>: \u201cTotal ionizing dose effects on a delay-based physical unclonable function implemented in fpgas,\u201d Electronics <b>7<\/b> (2018) 163 (DOI: 10.3390\/electronics7090163).","DOI":"10.3390\/electronics7090163"},{"key":"26","doi-asserted-by":"publisher","unstructured":"[26] S. Hou, <i>et al.<\/i>: \u201cA lightweight lfsr-based strong physical unclonable function design on fpga,\u201d IEEE Access <b>7<\/b> (2019) 64778 (DOI: 10.1109\/ACCESS.2019.2917259).","DOI":"10.1109\/ACCESS.2019.2917259"},{"key":"27","unstructured":"[27] N. A. Hazari, <i>et al.<\/i>: \u201cFpga ip obfuscation using ring oscillator physical unclonable function,\u201d NAECON 2018-IEEE National Aerospace and Electronics Conference (2018) 105 (DOI: 10.1109\/NAECON.2018.8556746)."},{"key":"28","unstructured":"[28] S. Srivathsa: Secure and energy efficient physical unclonable functions (2012)."},{"key":"29","doi-asserted-by":"publisher","unstructured":"[29] J. Kim, <i>et al.<\/i>: \u201cA physical unclonable function with redox-based nanoionic resistive memory,\u201d IEEE Trans. Inf. Forensics Security <b>13<\/b> (2018) 437 (DOI: 10.1109\/TIFS.2017.2756562).","DOI":"10.1109\/TIFS.2017.2756562"},{"key":"30","unstructured":"[30] K. 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