{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,8,19]],"date-time":"2023-08-19T20:34:14Z","timestamp":1692477254578},"reference-count":30,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"5","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2020]]},"DOI":"10.1587\/elex.17.20200032","type":"journal-article","created":{"date-parts":[[2020,2,16]],"date-time":"2020-02-16T22:04:16Z","timestamp":1581890656000},"page":"20200032-20200032","source":"Crossref","is-referenced-by-count":1,"title":["Proactive useless data flush architecture for nonvolatile SRAM using magnetic tunnel junctions"],"prefix":"10.1587","volume":"17","author":[{"given":"Daiki","family":"Kitagata","sequence":"first","affiliation":[{"name":"Laboratory for Future Interdisciplinary Research of Science and Technology, Tokyo Institute of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shuu\u2019ichirou","family":"Yamamoto","sequence":"additional","affiliation":[{"name":"Laboratory for Future Interdisciplinary Research of Science and Technology, Tokyo Institute of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Satoshi","family":"Sugahara","sequence":"additional","affiliation":[{"name":"Laboratory for Future Interdisciplinary Research of Science and Technology, Tokyo Institute of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","unstructured":"[1] S. Jain, <i>et al.<\/i>: \u201cA 280 mV-to-1.2 V wide-operating-range IA-32 processor in 32 nm CMOS,\u201d ISSCC Dig. Tech. Papers (2012) 66 (DOI: 10.1109\/ISSCC.2012.6176932)."},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] X. Dong, <i>et al.<\/i>: \u201cCircuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement,\u201d ACM\/IEEE Design Autom. Conf. (2008) 554.","DOI":"10.1145\/1391469.1391610"},{"key":"3","unstructured":"[3] X. Wu, <i>et al.<\/i>: \u201cPower and performance of read-write aware hybrid caches with non-volatile memories,\u201d Conf. on Design, Autom. and Test in Europe. European Design and Autom. Association (2009) 737 (DOI: 10.1109\/DATE.2009.5090762)."},{"key":"4","doi-asserted-by":"publisher","unstructured":"[4] X. Guo, <i>et al.<\/i>: \u201cResistive computation: Avoiding the power wall with low-leakage, STT-MRAM based computing,\u201d ACM SIGARCH Comput. Archit. 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Yamamoto, <i>et al.<\/i>: \u201cNonvolatile delay flip-flop using spin-transistor architecture with spin transfer torque MTJs for power-gating systems,\u201d Electron. Lett. <b>47<\/b> (2011) 1027 (DOI: 10.1049\/el.2011.1807).","DOI":"10.1049\/el.2011.1807"}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/17\/5\/17_17.20200032\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,3,14]],"date-time":"2020-03-14T03:30:54Z","timestamp":1584156654000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/17\/5\/17_17.20200032\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020]]},"references-count":30,"journal-issue":{"issue":"5","published-print":{"date-parts":[[2020]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.17.20200032","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020]]}}}