{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,3]],"date-time":"2022-04-03T07:43:54Z","timestamp":1648971834986},"reference-count":30,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"7","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2020]]},"DOI":"10.1587\/elex.17.20200056","type":"journal-article","created":{"date-parts":[[2020,3,15]],"date-time":"2020-03-15T22:04:33Z","timestamp":1584309873000},"page":"20200056-20200056","source":"Crossref","is-referenced-by-count":0,"title":["Mitigating multi-cell upsets impacts on approximate network on chip through unequal message protection"],"prefix":"10.1587","volume":"17","author":[{"given":"Jiajia","family":"Jiao","sequence":"first","affiliation":[{"name":"College of Information Engineering, Shanghai Maritime University"}]},{"given":"Dezhi","family":"Han","sequence":"additional","affiliation":[{"name":"College of Information Engineering, Shanghai Maritime University"}]}],"member":"532","reference":[{"key":"1","unstructured":"[1] J. Han and M. Orshansky: \u201cApproximate computing: An emerging paradigm for energy-efficient design,\u201d 2013 18th IEEE European Test Symposium (ETS) (2013) 1 (DOI: 10.1109\/ETS.2013.6569370)."},{"key":"2","doi-asserted-by":"publisher","unstructured":"[2] Q. Xu, <i>et al.<\/i>: \u201cApproximate computing: A survey,\u201d IEEE Des. Test <b>33<\/b> (2015) 8 (DOI: 10.1109\/MDAT.2015.2505723).","DOI":"10.1109\/MDAT.2015.2505723"},{"key":"3","doi-asserted-by":"publisher","unstructured":"[3] F. Betzel, <i>et al.<\/i>: \u201cApproximate communication: Techniques for reducing communication bottlenecks in large-scale parallel systems,\u201d ACM Comput. Surv. (CSUR) <b>51<\/b> (2018) 1 (DOI: 10.1145\/3145812).","DOI":"10.1145\/3145812"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] P. Bhamidipati: <i>RETUNES: Reliable and Energy-Efficient Network-on-Chip Architecture using Adaptive Routing and Approximate Communication<\/i> (Ohio University, 2019).","DOI":"10.1109\/ICCD.2018.00079"},{"key":"5","unstructured":"[5] M. F. Reza and P. Ampadu: \u201cApproximate communication strategies for energy-efficient and high performance NoC: Opportunities and challenges,\u201d Proc. of the 2019 on Great Lakes Symposium on VLSI (2019) 399 (DOI: 10.1145\/3299874.3319455)."},{"key":"6","doi-asserted-by":"publisher","unstructured":"[6] L. Wang, <i>et al.<\/i>: \u201cAn approximate bufferless network-on-chip,\u201d IEEE Access <b>7<\/b> (2019) 141516 (DOI: 10.1109\/ACCESS.2019.2943922).","DOI":"10.1109\/ACCESS.2019.2943922"},{"key":"7","unstructured":"[7] V. Y. Raparti and S. Pasricha: \u201cApproximate NoC and memory controller architectures for GPGPU accelerators,\u201d IEEE Trans. Parallel Distrib. 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ACM (2012) 37 (DOI: 10.1145\/FPGA.2145694.2145703)."}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/17\/7\/17_17.20200056\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,4,11]],"date-time":"2020-04-11T03:34:26Z","timestamp":1586576066000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/17\/7\/17_17.20200056\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020]]},"references-count":30,"journal-issue":{"issue":"7","published-print":{"date-parts":[[2020]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.17.20200056","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020]]}}}