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Chung, <i>et al.<\/i>: \u201cA 102dB-SFDR 16-bit calibration-free SAR ADC in 180-nm CMOS,\u201d IEEE APCCAS (2019) 5 (DOI: 10.1109\/APCCAS47518.2019.8953163)."},{"key":"2","unstructured":"[2] C. Rhee, <i>et al.<\/i>: \u201c8.4-to-16-bit resolution, 1-to-16 kHz bandwidth ADC with programmable-gain functionality for multi-sensor applications,\u201d Electron. Lett. <b>55<\/b> (2019) 982 (DOI: 10.1049\/el.2019.1496)."},{"key":"3","unstructured":"[3] S. Li, <i>et al.<\/i>: \u201cA 13-ENOB second-order noise-shaping SAR ADC realizing optimized NTF zeros using the error-feedback structure,\u201d IEEE J. Solid-State Circuits <b>53<\/b> (2018) 3484 (DOI: 10.1109\/JSSC.2018.2871081)."},{"key":"4","unstructured":"[4] A. Bannon, <i>et al.<\/i>: \u201cAn 18 b 5 MS\/s SAR ADC with 100.2 dB dynamic range,\u201d IEEE Symp. VLSI Circuits Dig. Tech. Papers (2014) 33 (DOI: 10.1109\/VLSIC.2014.6858371)."},{"key":"5","unstructured":"[5] D. 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