{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,1]],"date-time":"2026-02-01T04:10:45Z","timestamp":1769919045744,"version":"3.49.0"},"reference-count":31,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"9","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2020,5,15]]},"DOI":"10.1587\/elex.17.20200126","type":"journal-article","created":{"date-parts":[[2020,4,20]],"date-time":"2020-04-20T22:04:47Z","timestamp":1587420287000},"page":"20200126-20200126","source":"Crossref","is-referenced-by-count":5,"title":["An estimation method of timing mismatch error in hybrid filter bank DACs"],"prefix":"10.1587","volume":"17","author":[{"given":"Linglong","family":"Yin","sequence":"first","affiliation":[{"name":"School of Automation Engineering, University of Electronic Science and Technology of China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shulin","family":"Tian","sequence":"additional","affiliation":[{"name":"School of Automation Engineering, University of Electronic Science and Technology of China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ke","family":"Liu","sequence":"additional","affiliation":[{"name":"School of Automation Engineering, University of Electronic Science and Technology of China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Guangkun","family":"Guo","sequence":"additional","affiliation":[{"name":"School of Automation Engineering, University of Electronic Science and Technology of China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yindong","family":"Xiao","sequence":"additional","affiliation":[{"name":"School of Automation Engineering, University of Electronic Science and Technology of China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","unstructured":"[1] F. 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Anal. <b>2<\/b> (1965) 205 (DOI: 10.1137\/0702016)."}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/17\/9\/17_17.20200126\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,5,16]],"date-time":"2020-05-16T03:31:06Z","timestamp":1589599866000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/17\/9\/17_17.20200126\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,5,15]]},"references-count":31,"journal-issue":{"issue":"9","published-print":{"date-parts":[[2020]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.17.20200126","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,5,15]]}}}