{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,28]],"date-time":"2026-02-28T12:27:48Z","timestamp":1772281668632,"version":"3.50.1"},"reference-count":31,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"14","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2020,7,25]]},"DOI":"10.1587\/elex.17.20200197","type":"journal-article","created":{"date-parts":[[2020,6,24]],"date-time":"2020-06-24T22:06:31Z","timestamp":1593036391000},"page":"20200197-20200197","source":"Crossref","is-referenced-by-count":2,"title":["Phase-orthogonal FIR filters: An efficient VLSI architecture for communication applications"],"prefix":"10.1587","volume":"17","author":[{"given":"Punithavathi","family":"Duraiswamy","sequence":"first","affiliation":[{"name":"Department of Electronics and Communication Engineering, M S Ramaiah University of Applied Sciences"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Satishkumar","sequence":"additional","affiliation":[{"name":"Department of Electronics and Communication Engineering, M S Ramaiah University of Applied Sciences"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Raghu","sequence":"additional","affiliation":[{"name":"Department of Electronics and Communication Engineering, M S Ramaiah University of Applied Sciences"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shankar K.","family":"Selvaraja","sequence":"additional","affiliation":[{"name":"Center for Nano Science and Engineering, Indian Institute of Science"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","unstructured":"[1] H. Yang, <i>et al.<\/i>: \u201cCost-efficient IQ imbalance compensation scheme for DRM plus,\u201d IEICE Electron. Express <b>6<\/b> (2009) 743 (DOI: 10.1587\/elex.6.743)."},{"key":"2","unstructured":"[2] A. Balteanu, <i>et al.<\/i>: \u201cA high modulation bandwidth, 110 GHz power-DAC cell for IQ transmitter arrays with direct amplitude and phase modulation,\u201d IEEE J. Solid-State Circuits <b>49<\/b> (2014) 2103 (DOI: 10.1109\/jssc.2014.2327216)."},{"key":"3","unstructured":"[3] H. Jin, <i>et al.<\/i>: \u201cEfficient digital quadrature transmitter based on IQ cell sharing,\u201d IEEE J. Solid-State Circuits <b>52<\/b> (2017) 1345 (DOI: 10.1109\/jssc.2017.2655058)."},{"key":"4","unstructured":"[4] P. Kangaslahti, <i>et al.<\/i>: \u201cMiniature low noise G-band I-Q receiver,\u201d IEEE MTT-S International Microwave Symposium (2010) 1 (DOI: 10.1109\/mwsym.2010.5514912)."},{"key":"5","unstructured":"[5] A. Balteanu, <i>et al.<\/i>: \u201cA high modulation bandwidth, 110 GHz power-DAC cell for IQ transmitter arrays with direct amplitude and phase modulation,\u201d IEEE J. Solid-State Circuits (DOI: 10.1109\/jssc.2014.2327216)."},{"key":"6","unstructured":"[6] H. Jin, <i>et al.<\/i>: \u201cEfficient digital quadrature transmitter based on IQ cell sharing,\u201d IEEE J. Solid-State Circuits <b>52<\/b> (2017) 1345 (DOI: 10.1109\/jssc.2017.2655058)."},{"key":"7","unstructured":"[7] P. Kangaslahti, <i>et al.<\/i>: \u201cMiniature low noise G-band I-Q receiver,\u201d IEEE MTT-S International Microwave Symposium (2010) 1 (DOI: 10.1109\/mwsym.2010.5514912)."},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] D. Gabor: \u201cTheory of communications,\u201d Trans. Inst. Electr. Eng. <b>93<\/b> (1946) 429.","DOI":"10.1049\/ji-3-2.1946.0074"},{"key":"9","unstructured":"[9] P. Duraiswamy, <i>et al.<\/i>: \u201cEfficient implementation of 90\u00b0 phase shifter in FPGA,\u201d EURASIP Journal on Advances in Signal Processing <b>2011<\/b> (2011) 32 (DOI: 10.1186\/1687-6180-2011-32)."},{"key":"10","unstructured":"[10] R.N. Gorgui-Naguib and S.S. Dlay: \u201cHardware implementation of a Hilbert transformer,\u201d Proceedings of IEEE Mediterranean Electro-technical Conference (MELECON\u201991) (1991) 404 (DOI: 10.1109\/melcon.1991.161862)."},{"key":"11","unstructured":"[11] T. Cooklev and A. Nishihara: \u201cMaximally flat Hilbert transformers,\u201d Int. J. Circuit Theory Appl. <b>21<\/b> (1993) 563 (DOI: 10.1002\/cta.4490210607)."},{"key":"12","unstructured":"[12] J.G.R.C. Gomes and A. Petraglia: \u201cAn analog sampled-data DSB to SSB converter using recursive Hilbert transformer for accurate I and Q channel matching,\u201d IEEE Trans. Circuit Syst. II. Analog Digit. Signal Process. <b>49<\/b> (2002) 177 (DOI: 10.1109\/TCSII.2002.1013864)."},{"key":"13","unstructured":"[13] P. Duraiswamy, <i>et al.<\/i>: \u201cSynchronous delay based UWB pulse generator in FPGA,\u201d IEICE Electron. Express <b>9<\/b> (2012) 868 (DOI: 10.1587\/elex.9.868)."},{"key":"14","unstructured":"[14] W. Yin, <i>et al.<\/i>: \u201cFPGA-based expanded circuit design for dsp signal processing,\u201d 2014 Fifth International Conference on Intelligent Systems Design and Engineering Applications (2014) 511 (DOI: 10.1109\/isdea.2014.121)."},{"key":"15","unstructured":"[15] T. Arpitha, <i>et al.<\/i>: \u201cFPGA-GSM based gas leakage detection system,\u201d 2016 IEEE Annual India Conference (INDICON) (2016) 1 (DOI: 10.1109\/INDICON.2016.7838952)."},{"key":"16","unstructured":"[16] S.Y. Park and P.K. Meher: \u201cEfficient FPGA and ASIC realizations of a DA-based reconfigurable FIR Digital filter,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>61<\/b> (2014) 511 (DOI: 10.1109\/TCSII.2014.2324418)."},{"key":"17","unstructured":"[17] T. Pitchaiah, <i>et al.<\/i>: \u201cASIC realization of FIR digital filters -- A comparision study of power, area and delay for various architecures,\u201d 2015 13th International Conference on Electromagnetic Interference and Compatibility (INCEMIC) (2015) 259 (DOI: 10.1109\/INCEMIC.2015.8055891)."},{"key":"18","unstructured":"[18] C. Robert, <i>et al.<\/i>: \u201cLow power ASIC transmitter for UWB-IR radio communication and positioning,\u201d 2010 International Conference on Indoor Positioning and Indoor Navigation (2010) 1 (DOI: 10.1109\/IPIN.2010.5647856)."},{"key":"19","unstructured":"[19] R. Abhilash, <i>et al.<\/i>: \u201cAsic design of low power VLSI architecture for different multiplier algorithms using compressors,\u201d 2016 11th International Conference on Industrial and Information Systems (ICIIS) (2016) 387 (DOI: 10.1109\/ICIINFS.2016.8262971)."},{"key":"20","unstructured":"[20] A. Reilly, <i>et al.<\/i>: \u201cAnalytic signal generation-tips and traps,\u201d IEEE Trans. Signal Process. <b>42<\/b> (1994) 3241 (DOI: 10.1109\/78.330385)."},{"key":"21","unstructured":"[21] C.S. Turner: \u201cAn efficient analytic signal generator [DSP Tips &amp; Tricks],\u201d Signal Process. Mag. <b>26<\/b> (2009) 91 (DOI: 10.1109\/msp.2009.932794)."},{"key":"22","unstructured":"[22] G.D. Satishkumar, <i>et al.<\/i>: \u201cEfficient implementation of low mismatch IQ signal generator based on 90\u00b0 differential phase shifting,\u201d 2018 15th IEEE India Council International Conference (INDICON) (2018) 1 (DOI: 10.1109\/INDICON45594.2018.8987022)."},{"key":"23","unstructured":"[23] K.-H. Chen and T.-D. Chieueh: \u201cA low-power digit-based re-configurable FIR filter,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>53<\/b> (2006) 617 (DOI: 10.1109\/tcsii.2006.875373)."},{"key":"24","unstructured":"[24] D. Shi and Y.J. Yu: \u201cDesign of linear phase FIR filters with high probability of achieving minimum number of adders,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>58<\/b> (2011) 126 (DOI: 10.1109\/tcsi.2010.2055290)."},{"key":"25","unstructured":"[25] Y.J. Yu and Y.C. Lim: \u201cOptimization of linear phase FIR filters in dynamically expanding subexpressions space,\u201d Circuits, Syst., Signal Process. <b>29<\/b> (2010) 65 (DOI: 10.1007\/s00034-009-9114-7)."},{"key":"26","unstructured":"[26] K.D. Sadeghipoura and A. Abbaszadeh: \u201cEfficient realization of reconfigurable FIR filter using the new coefficient representation,\u201d IEICE Electron. Express <b>8<\/b> (2012) 902 (DOI: 10.1587\/elex.8.902)."},{"key":"27","unstructured":"[27] S. He and M. Torkelson: \u201cFPGA implementation of FIR filters using pipelined bit-serial canonical signed digit multipliers,\u201d Proceedings of IEEE Custom Integrated Circuits Conference (CICC\u201994) (1994) 81 (DOI: 10.1109\/cicc.1994.379762)."},{"key":"28","unstructured":"[28] H. Samueli: \u201cAn improved search algorithm for the design of multiplier less FIR filters with powers-of-two coefficients,\u201d IEEE Trans. Circuits Syst. <b>36<\/b> (1989) 1044 (DOI: 10.1109\/31.31347)."},{"key":"29","unstructured":"[29] A. Chandra and S. Chattopadhyay: \u201cDesign of hardware efficient FIR filter: a review of the state-of-the-art approaches,\u201d Eng. Sci. Technol. Int. J. <b>19<\/b> (2016) 212 (DOI: https:\/\/doi.org\/10.1016\/j.jestch.2015.06.006<i><\/i>)."},{"key":"30","unstructured":"[30] R.I. Hartley: \u201cSubexpression sharing in filters using canonic signed digit multipliers,\u201d IEEE Trans. Circuits Syst. II. Analog Digit. Signal Process. <b>43<\/b> (1996) 677 (DOI: http:\/\/dx.doi.org\/10.1109\/82.539000<i><\/i>)."},{"key":"31","unstructured":"[31] K. Chen, <i>et al.<\/i>: \u201cA low-power digit-based reconfigurable FIR filter,\u201d IEEE Trans. Circuits Syst. <b>53<\/b> (2006) 617 (DOI: http:\/\/dx.doi.org\/10.1109\/TCSII.2006.875373<i><\/i>)."}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/17\/14\/17_17.20200197\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,10,30]],"date-time":"2022-10-30T07:52:39Z","timestamp":1667116359000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/17\/14\/17_17.20200197\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,7,25]]},"references-count":31,"journal-issue":{"issue":"14","published-print":{"date-parts":[[2020]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.17.20200197","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,7,25]]}}}