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Lundstrom: \u201cDevice physics at the scaling limit: what matters? [MOSFETs],\u201d IEEE International Electron Devices Meeting (2003) 31 (DOI: 10.1109\/IEDM.2003.1269398)."},{"key":"2","unstructured":"[2] D.J. Frank, <i>et al.<\/i>: \u201cDevice scaling limits of Si MOSFETs and their application dependencies,\u201d Proc. IEEE <b>89<\/b> (2001) 259 (DOI: 10.1109\/5.915374)."},{"key":"3","unstructured":"[3] A. Padilla, <i>et al.<\/i>: \u201cFeedback FET: a novel transistor exhibiting steep switching behavior at low bias voltages,\u201d IEEE International Electron Devices Meeting (2008) 1 (DOI: 10.1109\/IEDM.2008.4796643)."},{"key":"4","unstructured":"[4] S. Hwang, <i>et al.<\/i>: \u201cSi<sub>1-<i>x<\/i><\/sub>Ge<sub><i>x<\/i><\/sub> positive feedback field-effect transistor with steep subthreshold swing for low-voltage operation,\u201d J. Semicond. Technol. Sci. <b>17<\/b> (2017) 216 (DOI: 10.5573\/JSTS.2017.17.2.216)."},{"key":"5","unstructured":"[5] K.-S. Li, <i>et al.<\/i>: \u201cSub-60mV-swing negative-capacitance FinFET without hysteresis,\u201d IEEE International Electron Devices Meeting (2015) 22 (DOI: 10.1109\/IEDM.2015.7409760)."},{"key":"6","unstructured":"[6] C.-I. Lin, <i>et al.<\/i>: \u201cEffects of the variation of ferroelectric properties on negative capacitance FET characteristics,\u201d IEEE Trans. Electron Devices <b>63<\/b> (2016) 2197 (DOI: 10.1109\/TED.2016.2514783)."},{"key":"7","unstructured":"[7] F.A. McGuire, <i>et al.<\/i>: \u201cSub-60 mV\/decade switching in 2D negative capacitance field-effect transistors with integrated ferroelectric polymer,\u201d Appl. Phys. Lett. <b>109<\/b> (2016) 93101 (DOI: 10.1063\/1.4961108)."},{"key":"8","unstructured":"[8] H. Kam, <i>et al.<\/i>: \u201cA new nano-electro-mechanical field effect transistor (NEMFET) design for low-power electronics,\u201d IEEE International Electron Devices Meeting (2005) 463 (DOI: 10.1109\/IEDM.2005.1609380)."},{"key":"9","unstructured":"[9] N. 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Lee, <i>et al.<\/i>: \u201cInvestigation of feasibility of tunneling field effect transistor (TFET) as highly sensitive and multi-sensing biosensors,\u201d J. Semicond. Technol. Sci. <b>17<\/b> (2017) 141 (DOI: 10.5573\/JSTS.2017.17.1.141)."},{"key":"14","unstructured":"[14] S. Park, <i>et al.<\/i>: \u201cImpact of the double-patterning technique on the LER-induced threshold voltage variation in symmetric tunnel field-effect transistor,\u201d IEICE Electron. Express <b>12<\/b> (2015) 20150349 (DOI: 10.1587\/elex.12.20150349)."},{"key":"15","unstructured":"[15] T. Tanamoto, <i>et al.<\/i>: \u201cSPICE simulation of 32-kHz crystal-oscillator operation based on Si tunnel TFET,\u201d IEICE Electron. Express <b>17<\/b> (2020) 20200025 (DOI: 10.1587\/elex.17.20200025)."},{"key":"16","unstructured":"[16] F. Mayer, <i>et al.<\/i>: \u201cImpact of SOI, Si<sub>1-<i>x<\/i><\/sub>Ge<sub><i>x<\/i><\/sub>OI and GeOI substrates on CMOS compatible tunnel FET performance,\u201d IEEE International Electron Devices Meeting (2008) 1 (DOI: 10.1109\/IEDM.2008.4796641)."},{"key":"17","unstructured":"[17] R. Gandhi, <i>et al.<\/i>: \u201cCMOS-compatible vertical-silicon-nanowire gate-all-around p-type tunneling FETs with &lt; 50-mV\/decade subthreshold swing,\u201d IEEE Electron Device Lett. <b>32<\/b> (2011) 1504 (DOI: 10.1109\/LED.2011.2165331)."},{"key":"18","unstructured":"[18] H.G. Virani and A. Kottantharayil: \u201cOptimization of hetero junction n-channel tunnel FET with high-k spacers,\u201d International Workshop on Electron Devices and Semiconductor Technology (2009) 1 (DOI: 10.1109\/EDST.2009.5166113)."},{"key":"19","unstructured":"[19] C. Anghel, <i>et al.<\/i>: \u201cTunnel field effect transistor with increased ON current, low-k spacer and high-k dielectric,\u201d Appl. Phys. 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Han, <i>et al.<\/i>: \u201cSilicon-based tunneling field-effect transistor with elevated germanium source formed on (110) silicon substrate,\u201d Appl. Phys. Lett <b>98<\/b> (2011) 153502 (DOI: 10.1063\/1.3579242)."},{"key":"24","unstructured":"[24] M. Kim, <i>et al.<\/i>: \u201cHigh I on\/I off Ge-source ultrathin body strained-SOI tunnel FETs,\u201d IEEE International Electron Devices Meeting (2014) 13.2.1 (DOI: 10.1109\/IEDM.2014.7047043)."},{"key":"25","unstructured":"[25] S. Takagi, <i>et al.<\/i>: \u201cIII-V and Ge\/strained SOI tunneling FET technologies for low power LSIs,\u201d Symposium on VLSI Technology (2015) T22 (DOI: 10.1109\/VLSIT.2015.7223687)."},{"key":"26","unstructured":"[26] T. Krishnamohan, <i>et al.<\/i>: \u201cDouble-gate strained-ge heterostructure tunneling FET (TFET) with record high drive currents and &lt;&lt;60mV\/dec subthreshold slope,\u201d IEEE International Electron Devices Meeting (2008) 1 (DOI: 10.1109\/IEDM.2008.4796839)."},{"key":"27","unstructured":"[27] G. Kim, <i>et al.<\/i>: \u201cHigh on-current Ge-channel heterojunction tunnel field-effect transistor using direct band-to-band tunneling,\u201d Micromachines <b>10<\/b> (2019) 77 (DOI: 10.3390\/mi10020077)."},{"key":"28","unstructured":"[28] E.-H. Toh, <i>et al.<\/i>: \u201cDevice physics and design of germanium tunneling field-effect transistor with source and drain engineering for low power and high performance applications,\u201d J. Appl. Phys. <b>103<\/b> (2008) 104504 (DOI: 10.1063\/1.2924413)."},{"key":"29","unstructured":"[29] M. Salmani-Jelodar, <i>et al.<\/i>: \u201cOptimum high-k oxide for the best performance of ultra-scaled double-gate MOSFETs,\u201d IEEE Trans. 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