{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T05:11:05Z","timestamp":1723180265188},"reference-count":30,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"19","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2020,10,10]]},"DOI":"10.1587\/elex.17.20200296","type":"journal-article","created":{"date-parts":[[2020,9,22]],"date-time":"2020-09-22T22:08:27Z","timestamp":1600812507000},"page":"20200296-20200296","source":"Crossref","is-referenced-by-count":6,"title":["A low-jitter 2.4 GHz all-digital MDLL with a dithering jitter reduction scheme for 256 times frequency multiplication"],"prefix":"10.1587","volume":"17","author":[{"given":"Dongjun","family":"Park","sequence":"first","affiliation":[{"name":"Electronic and Electrical Engineering, Hongik University"},{"name":"Samsung Electronics, System LSI"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jongsun","family":"Kim","sequence":"additional","affiliation":[{"name":"Electronic and Electrical Engineering, Hongik University"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","unstructured":"[1] N.D. Dalt, <i>et al.<\/i>: \u201cA compact triple-band low-jitter digital LC PLL with programmable coil in 130-nm CMOS,\u201d IEEE J. Solid-State Circuits <b>40<\/b> (2005) 1482 (DOI: 10.1109\/JSSC.2005.847325)."},{"key":"2","unstructured":"[2] N.D. Dalt: \u201cA design-oriented study of the nonlinear dynamics of digital bang-bang PLLs,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>52<\/b> (2005) 21 (DOI: 10.1109\/TCSI.2004.840089)."},{"key":"3","unstructured":"[3] R.B. Staszewski, <i>et al.<\/i>: \u201cAll-digital PLL and transmitter for mobile phones,\u201d IEEE J. Solid-State Circuits <b>40<\/b> (2005) 2469 (DOI: 10.1109\/JSSC.2005.857417)."},{"key":"4","unstructured":"[4] J. Lin, <i>et al.<\/i>: \u201cA PVT tolerant 0.18 MHz to 600 MHz self-calibrated digital PLL in 90 nm CMOS process,\u201d IEEE ISSCC Dig. Tech. Papers (2004) 488 (DOI: 10.1109\/ISSCC.2004.1332807)."},{"key":"5","unstructured":"[5] S.-Y. Yang, <i>et al.<\/i>: \u201cA 7.1 mW, 10 GHz all-digital frequency synthesizer with dynamically reconfigured digital loop filter in 90 nm CMOS technology,\u201d IEEE J. Solid-State Circuits <b>45<\/b> (2010) 578 (DOI: 10.1109\/JSSC.2009.2039530)."},{"key":"6","unstructured":"[6] J.A. Tierno, <i>et al.<\/i>: \u201cA wide power supply range, wide tuning range, all static CMOS all digital PLL in 65 nm SOI,\u201d IEEE J. Solid-State Circuits <b>43<\/b> (2008) 42 (DOI: 10.1109\/JSSC.2007.910966)."},{"key":"7","unstructured":"[7] E. Alon, <i>et al.<\/i>: \u201cReplica compensated linear regulators for supply-regulated phase-locked loops,\u201d IEEE J. Solid-State Circuits <b>41<\/b> (2006) 413 (DOI: 10.1109\/JSSC.2005.862347)."},{"key":"8","unstructured":"[8] A. Arakali, <i>et al.<\/i>: \u201cLow-power supply-regulation techniques for ring oscillators in phase-locked loops using a split-tuned architecture,\u201d IEEE J. Solid-State Circuits <b>44<\/b> (2009) 2169 (DOI: 10.1109\/JSSC.2009.2022916)."},{"key":"9","unstructured":"[9] K.K. Chang, <i>et al.<\/i>: \u201cA 0.44-Gb\/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs,\u201d IEEE J. Solid-State Circuits <b>38<\/b> (2003) 747 (DOI: 10.1109\/JSSC.2003.810045)."},{"key":"10","unstructured":"[10] W. Grollitsch, <i>et al.<\/i>: \u201cA 1.4 psrms-period-jitter TDC-less fractional-N digital PLL with digitally controlled ring oscillator in 65 nm CMOS,\u201d IEEE ISSCC Dig. Tech. Papers (2010) 478 (DOI: 10.1109\/ISSCC.2010.5433839)."},{"key":"11","unstructured":"[11] A. Elshazly, <i>et al.<\/i>: \u201cClock multiplication techniques using digital multiplying delay-locked loops,\u201d IEEE J. Solid-State Circuits <b>48<\/b> (2013) 1416 (DOI: 10.1109\/JSSC.2013.2254552)."},{"key":"12","unstructured":"[12] S. Kundu, <i>et al.<\/i>: \u201cA 0.2-1.45-GHz subsampling fractional-N digital MDLL with zero-offset aperture PD-based spur cancellation and in situ static phase offset detection,\u201d IEEE J. Solid-State Circuits <b>52<\/b> (2017) 799 (DOI: 10.1109\/JSSC.2016.2638432)."},{"key":"13","unstructured":"[13] G. Marucci, <i>et al.<\/i>: \u201cA 1.7 GHz MDLL-based fractional-N frequency synthesizer with 1.4ps RMS integrated jitter and 3 mW power using a 1b TDC,\u201d IEEE J. Solid-State Circuits <b>50<\/b> (2015) 2678 (DOI: 10.1109\/ISSCC.2014.6757469)."},{"key":"14","unstructured":"[14] R.K. Nandwana, <i>et al.<\/i>: \u201cA 1-to-2048 fully-integrated cascaded digital frequency synthesizer for low frequency reference clocks using scrambling TDC,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>64<\/b> (2017) 283 (DOI: 10.1109\/TCSI.2016.2609855)."},{"key":"15","unstructured":"[15] J. Kim and S. Han: \u201cA fast-locking all-digital Multiplying DLL for fractional-ratio dynamic frequency scaling,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>65<\/b> (2018) 276 (DOI: 10.1109\/TCSII.2017.2688369)."},{"key":"16","unstructured":"[16] H. Kim, <i>et al.<\/i>: \u201cA 2.4-GHz 1.5-mW digital multiplying delay-locked loop using pulsewidth comparator and double injection technique,\u201d IEEE J. Solid-State Circuits <b>52<\/b> (2017) 2934 (DOI: 10.1109\/JSSC.2017.2734910)."},{"key":"17","unstructured":"[17] B.M. Helal, <i>et al.<\/i>: \u201cA highly digital MDLL-based clock multiplier that leverages a self-scrambling time-to-digital converter to achieve subpicosecond jitter performance,\u201d IEEE J. Solid-State Circuits <b>43<\/b> (2008) 855 (DOI: 10.1109\/JSSC.2008.917372)."},{"key":"18","unstructured":"[18] Y.-K. Chiu and S.-I Liu: \u201cA PVT-tolerant MDLL using a frequency calibrator and a voltage monitor,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>27<\/b> (2019) 2698 (DOI: 10.1109\/TVLSI.2019.2925820)."},{"key":"19","unstructured":"[19] S. Kundu, <i>et al.<\/i>: \u201cA self-Calibrated 1.2-to-3.8GHz 0.0052mm2 synthesized fractional-N MDLL using a 2b time-period comparator in 22nm FinFET CMOS,\u201d 2020 IEEE International Solid-State Circuits Conference (2020) 276 (DOI: 10.1109\/ISSCC19947.2020.9062939)."},{"key":"20","unstructured":"[20] S. Levantino, <i>et al.<\/i>: \u201cA 1.7 GHz fractional-N frequency synthesizer based on a multiplying delay-locked loop,\u201d IEEE J. Solid-State Circuits <b>50<\/b> (2015) 2678 (DOI: 10.1109\/JSSC.2015.2473667)."},{"key":"21","unstructured":"[21] H. Hwang and J. Kim: \u201cA 100 Gb\/s quad-lane SerDes receiver with a PI-based quarter-rate all-digital CDR,\u201d Electronics <b>9<\/b> (2020) 1113 (DOI: 10.3390\/electronics9071113)."},{"key":"22","unstructured":"[22] G.-Y. Tak and K. Lee: \u201cA low-reference spur MDLL-based clock multiplier and derivation of discrete-time noise transfer function for phase noise analysis,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>65<\/b> (2018) 485 (DOI: 10.1109\/TCSI.2017.2719685)."},{"key":"23","unstructured":"[23] A. Santiccioli, <i>et al.<\/i>: \u201cA 1.6-to-3.0-GHz fractional-N MDLL with a digital-to-time converter range-reduction technique achieving 397fs jitter at 2.5-mW power,\u201d 2019 IEEE Custom Integrated Circuits Conference (2019) 1 (DOI: 10.1109\/CICC.2019.8780235)."},{"key":"24","unstructured":"[24] R. Farjad-Rad, <i>et al.<\/i>: \u201cA low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips,\u201d IEEE J. Solid-State Circuits <b>37<\/b> (2002) 1804 (DOI: 10.1109\/JSSC.2002.804340)."},{"key":"25","unstructured":"[25] T.A. Ali, <i>et al.<\/i>: \u201cA 4.6GHz MDLL with -46dBc reference spur and aperture position tuning,\u201d 2011 IEEE International Solid-State Circuits Conference (2011) 466 (DOI: 10.1109\/ISSCC.2011.5746400)."},{"key":"26","unstructured":"[26] J. Kim and B. Bae: \u201cAn anti-harmonic MDLL for phase aligned on-chip clock multiplication,\u201d IEICE Electron. Express <b>15<\/b> (2018) 1 (DOI: 10.1587\/elex.15.20180042)."},{"key":"27","unstructured":"[27] J. Kim and B.-H. Bae: \u201cA 2-4 GHz fast-locking frequency multiplying delay-locked loop,\u201d IEICE Electron. Express <b>14<\/b> (2017) 1 (DOI: 10.1587\/elex.13.20161056)."},{"key":"28","unstructured":"[28] B. Nikolic, <i>et al.<\/i>: \u201cImproved sense-amplifier-based flip-flop: design and measurements,\u201d IEEE J. Solid-State Circuits <b>35<\/b> (2000) 876 (DOI: 10.1109\/4.845191)."},{"key":"29","unstructured":"[29] V. Kratyuk, <i>et al.<\/i>: \u201cA digital PLL with stochastic time-to-digital converter,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>56<\/b> (2009) 1612 (DOI: 10.1109\/TCSI.2008.2010109)."},{"key":"30","unstructured":"[30] S. Pellerano, <i>et al.<\/i>: \u201cA 4.75-GHz fractional frequency divider-by-1.25 with TDC-based all-digital spur calibration in 45-nm CMOS,\u201d IEEE J. Solid-State Circuits <b>44<\/b> (2009) 3422 (DOI: 10.1109\/JSSC.2009.2032276)."}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/17\/19\/17_17.20200296\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,10,10]],"date-time":"2020-10-10T03:35:12Z","timestamp":1602300912000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/17\/19\/17_17.20200296\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,10,10]]},"references-count":30,"journal-issue":{"issue":"19","published-print":{"date-parts":[[2020]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.17.20200296","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,10,10]]}}}