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El-Nozahi, <i>et al.<\/i>: \u201cHigh PSR low drop-out regulator with feed-forward ripple cancellation technique,\u201d IEEE J. Solid-State Circuits <b>45<\/b> (2010) 565 (DOI: 10.1109\/JSSC.2009.2039685)."},{"key":"2","unstructured":"[2] J.-H. Wang, <i>et al.<\/i>: \u201cA low-dropout regulator with tail current control for DPWM clock correction,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>59<\/b> (2011) 45 (DOI: 10.1109\/TCSII.2011.2177703)."},{"key":"3","unstructured":"[3] C.-J. Park, <i>et al.<\/i>: \u201cExternal capacitor-less low drop-out regulator with 25 dB superior power supply rejection in the 0.4-4 MHz range,\u201d IEEE J. Solid-State Circuits <b>49<\/b> (2014) 486 (DOI: 10.1109\/JSSC.2013.2289897)."},{"key":"4","unstructured":"[4] Y. Lu, <i>et al.<\/i>: \u201cA fully-integrated low-dropout regulator with full-spectrum power supply rejection,\u201d IEEE Trans. Circuits Syst. I, Reg. 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Zhao, <i>et al.<\/i>: \u201cA digital LDO with Co-SA logics and TSPC dynamic latches for fast transient response,\u201d IEEE Solid-State Circuits Lett. <b>1<\/b> (2018) 154 (DOI: 10.1109\/LSSC.2018.2885217)."},{"key":"20","unstructured":"[20] S. Li and B.H. Calhoun: \u201c14.6 A 745pA hybrid asynchronous binary-searching and synchronous linear-searching digital LDO with 3.8<i>\u00d7<\/i>105 dynamic load range, 99.99% current efficiency, and 2mV output voltage ripple,\u201d ISSCC Dig. Tech. Papers (2019) 232 (DOI: 10.1109\/ISSCC.2019.8662533)."},{"key":"21","unstructured":"[21] M.A. Akram, <i>et al.<\/i>: \u201cCapacitorless self-clocked all-digital low-dropout regulator,\u201d IEEE J. Solid-State Circuits <b>54<\/b> (2019) 266 (DOI: 10.1109\/JSSC.2018.2871039)."},{"key":"22","unstructured":"[22] S.J. Yun, <i>et al.<\/i>: \u201cA digital LDO regulator with a self-clocking burst logic for ultralow power applications,\u201d IEEE Trans. Very Large Scale Integr. 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