{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,28]],"date-time":"2025-06-28T07:23:36Z","timestamp":1751095416482},"reference-count":31,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"20","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2020,10,25]]},"DOI":"10.1587\/elex.17.20200302","type":"journal-article","created":{"date-parts":[[2020,10,7]],"date-time":"2020-10-07T22:05:50Z","timestamp":1602108350000},"page":"20200302-20200302","source":"Crossref","is-referenced-by-count":2,"title":["A 12.5 Gbps clock and data recovery circuit with phase interpolation based digital locked loop"],"prefix":"10.1587","volume":"17","author":[{"given":"Gang","family":"Chen","sequence":"first","affiliation":[{"name":"School of Physical Science and Technology, University of Sichuan"},{"name":"Science and Technology on Analog Integrated Circuit Laboratory"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Min","family":"Gong","sequence":"additional","affiliation":[{"name":"School of Physical Science and Technology, University of Sichuan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chun","family":"Deng","sequence":"additional","affiliation":[{"name":"School of Physical Science and Technology, University of Sichuan"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","unstructured":"[1] M. Verbeke, <i>et al.<\/i>: \u201cA 1.8-pJ\/b, 12.5-25-Gb\/s wide range all-digital clock and data recovery circuit,\u201d IEEE J. Solid-State Circuits <b>53<\/b> (2018) 470 (DOI: 10.1109\/JSSC.2017.2755690)."},{"key":"2","unstructured":"[2] G. Shu, <i>et al.<\/i>: \u201cA 4-to-10.5 Gb\/s continuous-rate digital clock and data recovery with automatic frequency acquisition,\u201d IEEE J. Solid-State Circuits <b>51<\/b> (2016) 428 (DOI: 10.1109\/JSSC.2015.2497963)."},{"key":"3","unstructured":"[3] Z.-H. Hong, <i>et al.<\/i>: \u201cA 3.12 pJ\/bit, 19-27 Gbps receiver with 2-tap DFE embedded clock and data recovery,\u201d IEEE J. Solid-State Circuits <b>50<\/b> (2015) 2625 (DOI: 10.1109\/JSSC.2015.2475122)."},{"key":"4","unstructured":"[4] J.-Y. Kim, <i>et al.<\/i>: \u201cA 250-Mb\/s to 6-Gb\/s referenceless clock and data recovery circuit with clock frequency multiplier,\u201d IEEE Circuits Syst. II, Exp. Briefs <b>64<\/b> (2017) 650 (DOI: 10.1109\/TCSII.2015.2503721)."},{"key":"5","unstructured":"[5] N. Kalantari and J.F. Buckwalter: \u201cA multichannel serial link receiver with dual-loop clock-and-data recovery and channel equalization,\u201d IEEE Circuits Syst. I, Reg. Papers <b>60<\/b> (2013) 2920 (DOI: 10.1109\/TCSI.2013.2256172)."},{"key":"6","unstructured":"[6] W.-Y. Lee and L.-S. Kim: \u201cA 5.4-Gb\/s clock and data recovery circuit using seamless loop transition scheme with minimal phase noise degradation,\u201d IEEE Circuits Syst. I, Reg. Papers <b>59<\/b> (2012) 2518 (DOI: 10.1109\/TCSI.2012.2190678)."},{"key":"7","unstructured":"[7] C. Gimeno, <i>et al.<\/i>: \u201cMultilevel half-rate phase detector for clock and data recovery circuits,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>26<\/b> (2018) 1807 (DOI: 10.1109\/TVLSI.2018.2826440)."},{"key":"8","unstructured":"[8] T. Lee, <i>et al.<\/i>: \u201cA 5-Gb\/s digital clock and data recovery circuit with reduced DCO supply noise sensitivity utilizing coupling network,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>25<\/b> (2017) 380 (DOI: 10.1109\/TVLSI.2016.2566927)."},{"key":"9","unstructured":"[9] L.-H. Chiueh and T.-C. Lee: \u201cA 6-Gb\/s adaptive-loop-bandwidth clock and data recovery (CDR) circuit,\u201d IEEE Asian Solid State Circuits Conference (A-SSCC) (2014) 289 (DOI: 10.1109\/ASSCC.2014.7008917)."},{"key":"10","unstructured":"[10] T.-J. An, <i>et al.<\/i>: \u201cA 8.7mW 5-Gb\/s clock and data recovery circuit with 0.18-\u00b5m CMOS,\u201d IEEE International Symposium on Circuits and Systems (ISCAS) (2014) 2329 (DOI: 10.1109\/ISCAS.2014.6865638)."},{"key":"11","unstructured":"[11] S. Chen, <i>et al.<\/i>: \u201cA robust energy\/area-efficient forwarded-clock receiver with all-digital clock and data recovery in 28-nm CMOS for high-density interconnects,\u201d IEEE Circuits Syst. I, Reg. Papers <b>24<\/b> (2016) 578 (DOI: 10.1109\/TVLSI.2015.2409987)."},{"key":"12","unstructured":"[12] G. Wu, <i>et al.<\/i>: \u201cA 1-16-Gb\/s all-digital clock and data recovery with a wideband, high-linearity phase interpolator,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>24<\/b> (2016) 2511 (DOI: 10.1109\/TVLSI.2015.2508045)."},{"key":"13","unstructured":"[13] J.-M. Lin, <i>et al.<\/i>: \u201cA 2.5-Gb\/s DLL-based burst-mode clock and data recovery circuit with 4<i>\u00d7<\/i> oversampling,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>23<\/b> (2015) 791 (DOI: 10.1109\/TVLSI.2014.2316553)."},{"key":"14","unstructured":"[14] F.-T. Chen, <i>et al.<\/i>: \u201cA 10-Gb\/s low jitter single-loop clock and data recovery circuit with rotational phase frequency detector,\u201d IEEE Circuits Syst. I, Reg. Papers <b>61<\/b> (2014) 3278 (DOI: 10.1109\/TCSI.2014.2327291)."},{"key":"15","unstructured":"[15] Y.-H. Kwak, <i>et al.<\/i>: \u201cA 20 Gb\/s clock and data recovery with a ping-pong delay line for unlimited phase shifting in 65 nm CMOS process,\u201d IEEE Circuits Syst. I, Reg. Papers <b>60<\/b> (2013) 303 (DOI: 10.1109\/TCSI.2012.2215781)."},{"key":"16","unstructured":"[16] S.-H. Chu, <i>et al.<\/i>: \u201cA 22 to 26.5 Gb\/s optical receiver with all-digital clock and data recovery in a 65 nm CMOS process,\u201d IEEE J. Solid-State Circuits <b>50<\/b> (2015) 2603 (DOI: 10.1109\/JSSC.2015.2465843)."},{"key":"17","unstructured":"[17] S.H. Kim, <i>et al.<\/i>: \u201cA 3.125-to-22-Gb\/s multi-rate clock and data recovery using voltage-regulated active filter,\u201d IEICE Electron. Express <b>11<\/b> (2014) 20140953 (DOI: 10.1587\/elex.11.20140953)."},{"key":"18","unstructured":"[18] S. Chen, <i>et al.<\/i>: \u201cA robust energy\/area-efficient forwarded-clock receiver with all-digital clock and data recovery in 28-nm CMOS for high-density interconnects,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>24<\/b> (2016) 578 (DOI: 10.1109\/TVLSI.2015.2409987)."},{"key":"19","unstructured":"[19] H. Liu, <i>et al.<\/i>: \u201cA novel digital phase interpolation control for clock and data recovery circuit,\u201d IEICE Electron. Express <b>12<\/b> (2015) 20150617 (DOI: 10.1587\/elex.12.20150617)."},{"key":"20","unstructured":"[20] Y.-L. Lee, <i>et al.<\/i>: \u201cAn area- and power-efficient half-rate clock and data recovery circuit,\u201d IEEE International Symposium on Circuits and Systems (ISCAS) (2014) 2129 (DOI: 10.1109\/ISCAS.2014.6865588)."},{"key":"21","unstructured":"[21] H.-E. Liu, <i>et al.<\/i>: \u201cDesign an modeling of PLL-based clock and data recovery circuits with periodically embedded clock encoding for intra-panel interfaces,\u201d IEEE International Symposium on Circuits and Systems (ISCAS) (2016) 2234 (DOI: 10.1109\/ISCAS.2016.7539027)."},{"key":"22","unstructured":"[22] H.-J. Jeon, <i>et al.<\/i>: \u201cA bang-bang clock and data recovery using mixed mode adaptive loop gain strategy,\u201d IEEE J. Solid-State Circuits <b>48<\/b> (2013) 1398 (DOI: 10.1109\/JSSC.2013.2253414)."},{"key":"23","unstructured":"[23] M. Verbeke, <i>et al.<\/i>: \u201cInfluence of jitter on limit cycles in bang-bang clock and data recovery circuits,\u201d IEEE Circuits Syst. I, Reg. Papers <b>62<\/b> (2015) 1463 (DOI: 10.1109\/TCSI.2015.2415174)."},{"key":"24","unstructured":"[24] Y.-L. Lee, <i>et al.<\/i>: \u201cA 5 Gb\/s 1\/4-rate clock and data recovery circuit using dynamic stepwise bang-bang phase detector,\u201d IEEE Asian Solid State Circuits Conference (A-SSCC) (2012) 141 (DOI: 10.1109\/IPEC.2012.6522645)."},{"key":"25","unstructured":"[25] T. Lee and Y.-H. Ki: \u201cA 5-Gb\/s 2.67-mW\/Gb\/s digital clock and data recovery with hybrid dithering using a time-dithered delta-sigma modulator,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>24<\/b> (2016) 1450 (DOI: 10.1109\/TVLSI.2015.2449866)."},{"key":"26","unstructured":"[26] D.-H. Kwon, <i>et al.<\/i>: \u201cA clock and data recovery circuit with programmable multi-level phase detector characteristics and a built-in jitter monitor,\u201d IEEE Circuits Syst. I, Reg. Papers <b>62<\/b> (2015) 1472 (DOI: 10.1109\/TCSI.2015.2415180)."},{"key":"27","unstructured":"[27] G. Shu, <i>et al.<\/i>: \u201cA reference-less clock and data recovery circuit using phase-rotating phase-locked loop,\u201d IEEE J. Solid-State Circuits <b>49<\/b> (2014) 1036 (DOI: 10.1109\/JSSC.2013.2296152)."},{"key":"28","unstructured":"[28] T. Brtley, <i>et al.<\/i>: \u201cDelay window blind oversampling clock and data recovery algorithm with wide tracking range,\u201d IEEE International Symposium on Circuits and Systems (ISCAS) (2015) 1598 (DOI: 10.1109\/ISCAS.2015.7168954)."},{"key":"29","unstructured":"[29] H.S. Bindra, <i>et al.<\/i>: \u201cClock and data recovery module in 90nm for 10Gbps serial link with -18dB channel attenuation,\u201d IEEE International Symposium on Circuits and Systems (ISCAS) (2013) 2472 (DOI: 10.1109\/ISCAS.2013.6572380)."},{"key":"30","unstructured":"[30] K.-S. Kwak and O.-K. Kwon: \u201cPower-reduction technique using a single edge-tracking clock for multiphase clock and data recovery circuits,\u201d IEEE Circuits Syst. II, Exp. Briefs <b>61<\/b> (2014) 239 (DOI: 10.1109\/TCSII.2014.2305012)."},{"key":"31","unstructured":"[31] D.-H. Choi and C. Yoo: \u201cA 1.5-5.0 Gb\/s clock and data recovery circuit with dual-PFD phase-rotating phase locked loop,\u201d IEICE Electron. Express <b>11<\/b> (2014) 20140351 (DOI: 10.1587\/elex.11.20140351)."}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/17\/20\/17_17.20200302\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,10,31]],"date-time":"2020-10-31T03:35:03Z","timestamp":1604115303000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/17\/20\/17_17.20200302\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,10,25]]},"references-count":31,"journal-issue":{"issue":"20","published-print":{"date-parts":[[2020]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.17.20200302","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,10,25]]}}}