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(VLSI) Syst. <b>18<\/b> (2010) 1710 (DOI: 10.1109\/TVLSI.2009.2027907)."},{"key":"5","unstructured":"[5] G. Sun, <i>et al.<\/i>: \u201cA novel architecture of the 3D stacked MRAM L2 cache for CMPs,\u201d Proc. IEEE Int. Symp. High Performance Computer Architecture (2009) 239 (DOI: 10.1109\/HPCA.2009.4798259)."},{"key":"6","unstructured":"[6] S.P. Park, <i>et al.<\/i>: \u201cFuture cache design using STT MRAMs for improved energy efficiency: devices, circuits and architecture,\u201d Proc. ACM\/EDAC\/IEEE Design Automation Conf. (2012) 492 (DOI: 10.1145\/2228360.2228447)."},{"key":"7","unstructured":"[7] C.J. Lin, <i>et al.<\/i>: \u201c45nm low power CMOS logic compatible embedded STT MRAM utilizing a reverse-connection 1T\/1MTJ cell,\u201d Proc. IEEE Int. Electron Dev. Meeting (2009) 11.6.1 (DOI: 10.1109\/IEDM.2009.5424368)."},{"key":"8","unstructured":"[8] X. Fong, <i>et al.<\/i>: \u201cFailure mitigation techniques for 1T-1MTJ spin-transfer torque MRAM bit-cells,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>22<\/b> (2013) 384 (DOI: 10.1109\/TVLSI.2013.2239671)."},{"key":"9","unstructured":"[9] N.N. Mojumder, <i>et al.<\/i>: \u201cA three-terminal dual-pillar STT-MRAM for high-performance robust memory applications,\u201d IEEE Trans. Electron Devices <b>58<\/b> (2011) 1508 (DOI: 10.1109\/TED.2011.2116024)."},{"key":"10","unstructured":"[10] Y. Seo, <i>et al.<\/i>: \u201cDomain wall coupling-based STT-MRAM for on-chip cache applications,\u201d IEEE Trans. Electron Devices <b>62<\/b> (2015) 554 (DOI: 10.1109\/TED.2014.2377751)."},{"key":"11","unstructured":"[11] L. Liu, <i>et al.<\/i>: \u201cSpin-torque switching with the giant spin Hall effect of tantalum,\u201d Science <b>336<\/b> (2012) 555 (DOI: 10.1126\/science.1218197)."},{"key":"12","unstructured":"[12] C.-F. Pai, <i>et al.<\/i>: \u201cSpin transfer torque devices utilizing the giant spin Hall effect of tungsten,\u201d Applied Physics Lett. <b>101<\/b> (2012) 122404 (DOI: 10.1063\/1.4753947)."},{"key":"13","unstructured":"[13] T. Jungwirth, <i>et al.<\/i>: \u201cSpin Hall effect devices,\u201d Nature Materials <b>11<\/b> (2012) 382 (DOI: 10.1038\/NMAT3279)."},{"key":"14","unstructured":"[14] P. Gambardella and I.M. Miron: \u201cCurrent-induced spin-orbit torques,\u201d Phil. Trans. R. Soc. A <b>369<\/b> (2011) 3175 (DOI: 10.1098\/rsta.2010.0336)."},{"key":"15","unstructured":"[15] I.M. Miron, <i>et al.<\/i>: \u201cPerpendicular switching of a single ferromagnetic layer induced by in-plane current injection,\u201d Nature <b>476<\/b> (2011) 189 (DOI: 10.1038\/nature10309)."},{"key":"16","unstructured":"[16] A. Hoffmann: \u201cSpin Hall effects in metals,\u201d IEEE Trans. Mag. <b>49<\/b> (2013) 5172 (DOI: 10.1109\/TMAG.2013.2262947)."},{"key":"17","unstructured":"[17] Y. Seo, <i>et al.<\/i>: \u201cArea-efficient SOT-MRAM with a Schottky diode,\u201d IEEE Electron Device Lett. <b>37<\/b> (2016) 982 (DOI: 10.1109\/LED.2016.2578959)."},{"key":"18","unstructured":"[18] Y. Seo and K. Roy: \u201cHigh-density SOT-MRAM based on shared bitline structure,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>26<\/b> (2018) 1600 (DOI: 10.1109\/TVLSI.2018.2822841)."},{"key":"19","unstructured":"[19] H. Ulrichs, <i>et al.<\/i>: \u201cOptimization of Pt-based spin-Hall-effect spintronic devices,\u201d Applied Physics Lett. <b>13<\/b> (2013) 132402 (DOI: 10.1063\/1.4799492)."},{"key":"20","unstructured":"[20] Y. Kim, <i>et al.<\/i>: \u201cMultilevel spin-orbit torque MRAMs,\u201d IEEE Trans. Electron Devices <b>62<\/b> (2015) 561 (DOI: 10.1109\/TED.2014.2377721)."},{"key":"21","unstructured":"[21] http:\/\/www.mosis.com\/Technical\/Designrules\/scmos\/."},{"key":"22","unstructured":"[22] S.K. Gupta, <i>et al.<\/i>: \u201cLayout-aware optimization of STT-MRAMs,\u201d Proc. Design, Automation &amp; Test in Europe Conf. (2012) 1455 (DOI: 10.1109\/date.2012.6176595)."},{"key":"23","unstructured":"[23] L. Liebman: \u201cDfM, the teenage years,\u201d Proc. SPIE (2008) 692502 (DOI: 10.1117\/12.782650)."},{"key":"24","unstructured":"[24] T. Pompl, <i>et al.<\/i>: \u201cPractical aspects of reliability analysis for IC designs,\u201d Proc. ACM\/ IEEE Design Automat. Conf. (2006) 193 (DOI: 10.1145\/1146909.1146962)."},{"key":"25","unstructured":"[25] X. Fong, <i>et al.<\/i>: \u201cKNACK: a hybrid spin-charge mixed-mode simulator for evaluating different genres of spin transfer torque MRAM bit-cells,\u201d Proc. Int. Conf. Simul. Semicond. Process. Devices (2011) 51 (DOI: 10.1109\/SISPAD.2011.6035047)."},{"key":"26","unstructured":"[26] J.C. Slonczewski: \u201cCurrent-driven excitation of magnetic multilayers,\u201d J. Magnetism and Magnetic Materials <b>159<\/b> (1996) L1 (DOI: 10.1016\/0304-8853(96)00062-5)."},{"key":"27","unstructured":"[27] J. Xiao, <i>et al.<\/i>: \u201cMacrospin models of spin transfer dynamics,\u201d Physical Review B <b>72<\/b> (2005) 014446 (DOI: 10.1103\/PhysRevB.72.014446)."},{"key":"28","unstructured":"[28] HSPICE, http:\/\/www.synopsys.com\/Tools\/Verification\/AMSVerification\/CircuitSimulation\/HSPICE\/"},{"key":"29","unstructured":"[29] Y. Shang, <i>et al.<\/i>: \u201cAnalysis and modeling of internal state variables for dynamic effects of nonvolatile memory devices,\u201d IEEE Trans. Circuits Syst. I, Reg, Papers <b>59<\/b> (2012) 1906 (DOI: 10.1109\/TCSI.2011.2180441)."},{"key":"30","unstructured":"[30] T. Kishi, <i>et al.<\/i>: \u201cLower-current and fast switching of a perpendicular TMR for high speed and high density spin-transfer-torque MRAM,\u201d Proc. IEEE Int. Electron Dev. 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