{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,1]],"date-time":"2025-11-01T20:23:11Z","timestamp":1762028591683,"version":"build-2065373602"},"reference-count":31,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"24","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2020,12,25]]},"DOI":"10.1587\/elex.17.20200391","type":"journal-article","created":{"date-parts":[[2020,12,6]],"date-time":"2020-12-06T22:06:25Z","timestamp":1607292385000},"page":"20200391-20200391","source":"Crossref","is-referenced-by-count":0,"title":["A full matrix joint optimization method for hardware implementation of AES MixColumns\/InvMixColumns"],"prefix":"10.1587","volume":"17","author":[{"given":"Xiaoqiang","family":"ZHANG","sequence":"first","affiliation":[{"name":"Key Laboratory of Advanced Perception and Intelligent Control of High-end Equipment, Ministry of Education"},{"name":"College of Electrical Engineering, Anhui Polytechnic University"},{"name":"School of Electronic Science and Engineering, Nanjing University"}]},{"given":"Fan","family":"YANG","sequence":"additional","affiliation":[{"name":"Key Laboratory of Advanced Perception and Intelligent Control of High-end Equipment, Ministry of Education"},{"name":"College of Electrical Engineering, Anhui Polytechnic University"}]},{"given":"Xinxing","family":"ZHENG","sequence":"additional","affiliation":[{"name":"College of Information Engineering, Wuhu Institute of Technology"}]},{"given":"Xinggan","family":"ZHANG","sequence":"additional","affiliation":[{"name":"School of Electronic Science and Engineering, Nanjing University"}]},{"given":"Ning","family":"WU","sequence":"additional","affiliation":[{"name":"College of Electronic and Information Engineering, Nanjing University of Aeronautics and Astronautics"}]}],"member":"532","reference":[{"key":"1","unstructured":"[1] National Institute of Standards and Technology (NIST): Advanced Encryption Standard (AES) FIPS Publication 197 (2001) http:\/\/csrc.nist.gov\/publications\/fips\/fips197\/fips-197.pdf."},{"key":"2","unstructured":"[2] M.M. Wong, <i>et al.<\/i>: \u201cComposite field GF(((2<sup>2<\/sup>)<sup>2<\/sup>)<sup>2<\/sup>) Advanced Encryption Standard (AES) S-box with algebraic normal form representation in the subfield inversion,\u201d IET Circuits Dev. Syst. <b>5<\/b> (2011) 471 (DOI: 10.1049\/iet-cds.2010.0435)."},{"key":"3","unstructured":"[3] M.M. Wong, <i>et al.<\/i>: \u201cConstruction of optimum composite field architecture for compact high-throughput AES S-boxes,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>20<\/b> (2012) 1151 (DOI: 10.1109\/TVLSI.2011.2141693)."},{"key":"4","unstructured":"[4] X. Zhang and K.K. Parhi: \u201cImplementation approaches for the advanced encryption standard algorithm,\u201d IEEE Circuits and Systems Magazine <b>2<\/b> (2002) 24 (DOI: 10.1109\/MCAS.2002.1173133)."},{"key":"5","unstructured":"[5] Y.-K. Lai, <i>et al.<\/i>: \u201cA novel memoryless AES cipher architecture for networking applications,\u201d Proc. IEEE Int. Symposium on Circuits and Systems (ISCAS\u201904) (2004) IV-333 (DOI: 10.1109\/ISCAS.2004.1329008)."},{"key":"6","unstructured":"[6] H. Kuo and I. Verbauwhede: \u201cArchitectural optimization for a 1.82Gbits\/sec VLSI implementation of the AES Rijndael algorithm,\u201d Proceedings CHES (2001) 51 (DOI: 10.1007\/3-540-44709-1_6)."},{"key":"7","unstructured":"[7] C.-C. Lu and S.-Y. Tseng: \u201cIntegrated design of AES (Advanced Encryption Standard) encrypter and decrypter,\u201d IEEE International Conference on Application-Specific Systems, Architectures and Processors (2002) 277 (DOI: 10.1109\/ASAP.2002.1030726)."},{"key":"8","unstructured":"[8] X. Zhang and K.K. Parhi: \u201cHigh-speed VLSI architectures for the AES algorithm,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>12<\/b> (2004) 957 (DOI: 10.1109\/TVLSI.2004.832943)."},{"key":"9","unstructured":"[9] V. Fischer: \u201cRealization of the round 2 candidates using altera FPGA,\u201d The Third AES Conference (AES3) (2000)."},{"key":"10","unstructured":"[10] C.-Y. Li, <i>et al.<\/i>: \u201cAn efficient area-delay product design for MixColumns\/InvMixColumns in AES,\u201d IEEE Computer Society Annual Symposium on VLSI (2008) 503 (DOI: 10.1109\/ISVLSI.2008.81)."},{"key":"11","unstructured":"[11] V. Fischer, <i>et al.<\/i>: \u201cInvMixColumn decomposition and multilevel resource sharing in AES implementations,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>13<\/b> (2005) 989 (DOI: 10.1109\/TVLSI.2005.853606)."},{"key":"12","unstructured":"[12] H. Li and Z. Friggstad: \u201cAn efficient architecture for the AES mix columns operation,\u201d IEEE International Symposium on Circuits &amp; Systems (2005) 4637 (DOI: 10.1109\/ISCAS.2005.1465666)."},{"key":"13","unstructured":"[13] Y.Q. Zhong, <i>et al.<\/i>: \u201cA low-cost and high efficiency architecture of AES crypto-engine,\u201d China Communications <b>2<\/b> (2008) 8 (DOI: 10.1109\/CHINACOM.2007.4469389)."},{"key":"14","unstructured":"[14] E.G. Ahmed, <i>et al.<\/i>: \u201cLightweight mix columns implementation for AES,\u201d MMACTEE\u201909: Proceedings of the 11th WSEAS International Conference on Mathematical Methods and Computational Techniques in Electrical Engineering (2009) 48."},{"key":"15","unstructured":"[15] A. Hosangadi, <i>et al.<\/i>: \u201cSimultaneous optimization of delay and number of operations in multiplierless implementation of linear systems,\u201d 14th International Workshop on Logic and Synthesis-IWLS (2005) 1."},{"key":"16","unstructured":"[16] R. Mahesh and A.P. Vinod: \u201cNew reconfigurable architectures for implementing FIR filters with low complexity,\u201d IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. <b>29<\/b> (2010) 275 (DOI: 10.1109\/TCAD.2009.2035548)."},{"key":"17","unstructured":"[17] M. Mart\u00ednez-Peir\u00f3, <i>et al.<\/i>: \u201cDesign of high-speed multiplierless filters using a nonrecursive signed common subexpression algorithm,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>49<\/b> (2002) 196 (DOI: 10.1109\/TCSII.2002.1013866)."},{"key":"18","unstructured":"[18] F. Al-Hasani, <i>et al.<\/i>: \u201cA common subexpression elimination tree algorithm,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>60<\/b> (2013) 2389 (DOI: 10.1109\/TCSI.2013.2244328)."},{"key":"19","unstructured":"[19] R. Mahesh and A.P. Vinod: \u201cA new common subexpression elimination algorithm for realizing low-complexity higher order digital filters,\u201d IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. <b>27<\/b> (2008) 217 (DOI: 10.1109\/TCAD.2007.907064)."},{"key":"20","unstructured":"[20] N. Chen and Z.Y. Yan: \u201cHigh-performance designs of AES transformations,\u201d 2009 IEEE International Symposium on Circuits and Systems - ISCAS (2009) 2906 (DOI: 10.1109\/ISCAS.2009.5118410)."},{"key":"21","unstructured":"[21] M.M. Wong and M.L.D. Wong: \u201cA new common subexpression elimination algorithm with application in composite field AES S-box,\u201d 10th International Conference on Information Sciences, Signal Processing and their Applications (ISSPA 2010) (2010) 452 (DOI: 10.1109\/ISSPA.2010.5605445)."},{"key":"22","unstructured":"[22] X. Zhang, <i>et al.<\/i>: \u201cAn optimized delay-aware common subexpression elimination algorithm for hardware implementation of binary field linear transform,\u201d IEICE Electron. Express <b>11<\/b> (2014) 20140934 (DOI: 10.1587\/elex.11.20140934)."},{"key":"23","unstructured":"[23] C. Paar: \u201cOptimized arithmetic for Reed-Solomon encoders,\u201d Proc. IEEE Int. Sym. Information Theory (1997) 250 (DOI: 10.1109\/ISIT.1997.613165)."},{"key":"24","unstructured":"[24] N. Chen and Z.Y. Yan: \u201cCyclotomic FFTs with reduced additive complexities based on a novel common subexpression elimination algorithm,\u201d IEEE Trans. Signal Process. <b>57<\/b> (2009) 1010 (DOI: 10.1109\/TSP.2008.2009891)."},{"key":"25","unstructured":"[25] Y. Lee, <i>et al.<\/i>: \u201cLow-complexity parallel Chien search structure using two-dimensional optimization,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>58<\/b> (2011) 522 (DOI: 10.1109\/TCSII.2011.2158709)."},{"key":"26","unstructured":"[26] X. Zhang, <i>et al.<\/i>: \u201cLow-delay parallel Chien search architecture for RS decoder,\u201d IEICE Electron. Express <b>13<\/b> (2016) 20160729 (DOI: 10.1587\/elex.13.20160729)."},{"key":"27","unstructured":"[27] J.L. Imana, <i>et al.<\/i>: \u201cBit-parallel finite field multipliers for irreducible trinomials,\u201d IEEE Trans. Comput. <b>55<\/b> (2006) 520 (DOI: 10.1109\/TC.2006.69)."},{"key":"28","unstructured":"[28] X. Zhang, <i>et al.<\/i>: \u201cOptimization of area and delay for implementation of the composite field advanced encryption standard S-box,\u201d J. Circuits Syst. Comput. <b>25<\/b> (2016) 1650037 (DOI: 10.1142\/S0218126616500377)."},{"key":"29","unstructured":"[29] X. Zhang, <i>et al.<\/i>: \u201cA low critical path delay structure for composite field AES S-box based on constant matrices multiplication merging,\u201d IEICE Electron. Express <b>17<\/b> (2020) 20200035 (DOI: 10.1587\/elex.17.20200035)."},{"key":"30","unstructured":"[30] N. Petra, <i>et al.<\/i>: \u201cA novel architecture for Galois fields <i>GF<\/i>(2<i><sup>m<\/sup><\/i>) multipliers based on Mastrovito scheme,\u201d IEEE Trans. Comput. <b>56<\/b> (2007) 1470 (DOI: 10.1109\/TC.2007.70741)."},{"key":"31","unstructured":"[31] A.P. Chandrakasan, <i>et al.<\/i>: \u201cOptimizing power using transformations,\u201d IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. <b>14<\/b> (1995) 12 (DOI: 10.1109\/43.363126)."}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/17\/24\/17_17.20200391\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,12,26]],"date-time":"2020-12-26T03:25:38Z","timestamp":1608953138000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/17\/24\/17_17.20200391\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,12,25]]},"references-count":31,"journal-issue":{"issue":"24","published-print":{"date-parts":[[2020]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.17.20200391","relation":{},"ISSN":["1349-2543"],"issn-type":[{"type":"electronic","value":"1349-2543"}],"subject":[],"published":{"date-parts":[[2020,12,25]]}}}