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Volder, <i>et al.<\/i>: \u201cThe CORDIC trigonometric computing technique,\u201d IRE Trans. Electronic Computers <b>EC-8<\/b> (1959) 330 (DOI: 10.1109\/TEC.1959.5222693)."},{"key":"2","unstructured":"[2] L. Chen, <i>et al.<\/i>: \u201cAlgorithm and design of a fully parallel approximate coordinate rotation digital computer (CORDIC),\u201d IEEE Trans. Multi-Scale Comput. Syst. <b>3<\/b> (2017) 139 (DOI: 10.1109\/TMSCS.2017.2696003)."},{"key":"3","unstructured":"[3] M. Garrido, <i>et al.<\/i>: \u201cCORDIC II: A new improved CORDIC algorithm,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>63<\/b> (2016) 186 (DOI: 10.1109\/TCSII.2015.2483422)."},{"key":"4","unstructured":"[4] E. Antelo, <i>et al.<\/i>: \u201cA low-latency pipelined 2D and 3D CORDIC processors,\u201d IEEE Trans. Comput. <b>57<\/b> (2008) 404 (DOI: 10.1109\/TC.2007.70796)."},{"key":"5","unstructured":"[5] M.G.B. Sumanasena, <i>et al.<\/i>: \u201cA scale factor correction scheme for the CORDIC algorithm,\u201d IEEE Trans. Comput. <b>57<\/b> (2008) 1148 (DOI: 10.1109\/TC.2008.41)."},{"key":"6","unstructured":"[6] R. Shukla, <i>et al.<\/i>: \u201cLow latency hybrid CORDIC algorithm,\u201d IEEE Trans. Comput. <b>63<\/b> (2014) 3066 (DOI: 10.1109\/TC.2013.173)."},{"key":"7","unstructured":"[7] T.Y. Sung, <i>et al.<\/i>: \u201cDesign and simulation of reusable IP CORDIC core for special-purpose processors,\u201d IET Computers &amp; Digital Techniques <b>1<\/b> (2007) 581 (DOI: 10.1049\/iet-cdt:20060075)."},{"key":"8","unstructured":"[8] L. Vachhani, <i>et al.<\/i>: \u201cEfficient FPGA realization of CORDIC with application to robotic exploration,\u201d IEEE Trans. Ind. Electron. <b>56<\/b> (2009) 4915 (DOI: 10.1109\/TIE.2009.2026225)."},{"key":"9","unstructured":"[9] A.N. Sapper, <i>et al.<\/i>: \u201cExploring the combination of number of bits and number of iterations for a power-efficient fixed-point CORDIC implementation,\u201d IEEE International Conference on Electronics, Circuits and Systems (ICECS) (2017) 302 (DOI: 10.1109\/ICECS.2017.8292079)."},{"key":"10","unstructured":"[10] S. Aggarwal, <i>et al.<\/i>: \u201cConcept, design, and implementation of reconfigurable CORDIC,\u201d IEEE Trans. Very Large Scale Integr. Syst. <b>24<\/b> (2016) 1588 (DOI: 10.1109\/TVLSI.2015.2445855)."},{"key":"11","unstructured":"[11] K.C. Ray, <i>et al.<\/i>: \u201cCORDIC-based unified VLSI architecture for implementing window functions for real time spectral analysis,\u201d IEE Proceedings - Circuits, Devices and Systems <b>153<\/b> (2006) 539 (DOI: 10.1049\/ip-cds:20050280)."},{"key":"12","unstructured":"[12] Y. Liu, <i>et al.<\/i>: \u201cA modified CORDIC FPGA implementation for wave generation,\u201d Circuits, Systems, and Signal Processing <b>33<\/b> (2014) 321 (DOI: 10.1007\/s00034-013-9638-8)."},{"key":"13","unstructured":"[13] H. Mahdavi, <i>et al.<\/i>: \u201cArea-time-power efficient FFT architectures based on binary-signed-digit CORDIC,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>66<\/b> (2019) 3874 (DOI: 10.1109\/TCSI.2019.2922988)."},{"key":"14","unstructured":"[14] J. Chen, <i>et al.<\/i>: \u201cConfigurable floating-point FFT accelerator on FPGA based multiple-rotation CORDIC,\u201d Chinese Journal of Electronics <b>25<\/b> (2016) 1063 (DOI: 10.1049\/cje.2016.08.002)."},{"key":"15","unstructured":"[15] H. Huang, <i>et al.<\/i>: \u201cCORDIC based fast Radix-2 DCT algorithm,\u201d IEEE Signal Process. Lett. <b>20<\/b> (2013) 483 (DOI: 10.1109\/LSP.2013.2252616)."},{"key":"16","unstructured":"[16] M. Lee, <i>et al.<\/i>: \u201cReconfigurable CORDIC-based low-power DCT architecture based on data priority,\u201d IEEE Trans. Very Large Scale Integr. Syst. <b>22<\/b> (2014) 1060 (DOI: 10.1109\/TVLSI.2013.2263232)."},{"key":"17","unstructured":"[17] D. De Caro, <i>et al.<\/i>: \u201cA 380 MHz direct digital synthesizer\/mixer with hybrid CORDIC architecture in 0.25 um CMOS,\u201d IEEE J. Solid-State Circuits <b>42<\/b> (2007) 151 (DOI: 10.1109\/JSSC.2006.886527)."},{"key":"18","unstructured":"[18] H. Lee, <i>et al.<\/i>: \u201cEfficient low-latency implementation of CORDIC-based sorted QR decomposition for multi-Gbps MIMO systems,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>65<\/b> (2018) 1375 (DOI: 10.1109\/TCSII.2018.2853099)."},{"key":"19","unstructured":"[19] P.K. Meher, <i>et al.<\/i>: \u201c50 years of CORDIC: algorithms, architectures, and applications,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>56<\/b> (2009) 1893 (DOI: 10.1109\/tcsi.2009.2025803)."},{"key":"20","unstructured":"[20] J. Duprat, <i>et al.<\/i>: \u201cThe CORDIC algorithm: new results for fast VLSI implementation,\u201d IEEE Trans. Comput. <b>42<\/b> (1993) 168 (DOI: 10.1109\/12.204786)."},{"key":"21","unstructured":"[21] Y.H. Hu, <i>et al.<\/i>: \u201cCORDIC-based VLSI architectures for digital signal processing,\u201d IEEE Signal Process. Mag. <b>9<\/b> (1992) 16 (DOI: 10.1109\/79.143467)."},{"key":"22","unstructured":"[22] H.T. Nguyen, <i>et al.<\/i>: \u201cA high-throughput low-energy arithmetic processor,\u201d IEICE Trans. Electron. <b>E101-C<\/b> (2018) 281 (DOI: 10.1587\/transele.E101.C.281)."},{"key":"23","unstructured":"[23] P.K. Meher, <i>et al.<\/i>: \u201cCORDIC designs for fixed angle of rotation,\u201d IEEE Trans. Very Large Scale Integr. Syst. <b>21<\/b> (2013) 217 (DOI: 10.1109\/TVLSI.2012.2187080)."},{"key":"24","unstructured":"[24] R. Ramadoss, <i>et al.<\/i>: \u201cReliable hardware architectures of the CORDIC algorithm with a fixed angle of rotations,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>64<\/b> (2017) 972 (DOI: 10.1109\/TCSII.2016.2624508)."},{"key":"25","unstructured":"[25] C.S. Wu, <i>et al.<\/i>: \u201cA high-performance\/low-latency vector rotational CORDIC architecture based on extended elementary angle set and trellis-based searching schemes,\u201d IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process. <b>50<\/b> (2003) 589 (DOI: 10.1109\/TCSII.2003.816923)."},{"key":"26","unstructured":"[26] Y.H. Hu, <i>et al.<\/i>: \u201cAn angle recoding method for CORDIC algorithm implementation,\u201d IEEE Trans. Comput. <b>42<\/b> (1993) 99 (DOI: 10.1109\/12.192217)."},{"key":"27","unstructured":"[27] B. Lakshmi, <i>et al.<\/i>: \u201cVLSI architecture for parallel radix-4 CORDIC,\u201d Microprocessors &amp; Microsystems <b>37<\/b> (2013) 79 (DOI: 10.1016\/j.micpro.2012.12.001)."},{"key":"28","unstructured":"[28] A. Changela, <i>et al.<\/i>: \u201cFPGA implementation of high-performance, resource-efficient Radix-16 CORDIC rotator based FFT algorithm,\u201d Integration the VLSI Journal <b>73<\/b> (2020) 89 (DOI: 10.1016\/j.vlsi.2020.03.008)."},{"key":"29","unstructured":"[29] F.J. Jaime, <i>et al.<\/i>: \u201cEnhanced scaling-free CORDIC,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>57<\/b> (2010) 1654 (DOI: 10.1109\/TCSI.2009.2037391)."},{"key":"30","unstructured":"[30] S. Aggarwal, <i>et al.<\/i>: \u201cArea-time efficient scaling-free CORDIC using generalized micro-rotation selection,\u201d IEEE Trans. Very Large Scale Integr. Syst. <b>20<\/b> (2012) 1542 (DOI: 10.1109\/TVLSI.2011.2158459)."},{"key":"31","unstructured":"[31] K. Maharatna, <i>et al.<\/i>: \u201cModified virtually scaling-free adaptive CORDIC rotator algorithm and architecture,\u201d IEEE Trans. Circuits Syst. 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