{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,15]],"date-time":"2026-04-15T06:59:53Z","timestamp":1776236393124,"version":"3.50.1"},"reference-count":30,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"2","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2021,1,25]]},"DOI":"10.1587\/elex.17.20200420","type":"journal-article","created":{"date-parts":[[2020,12,22]],"date-time":"2020-12-22T22:08:11Z","timestamp":1608674891000},"page":"20200420-20200420","source":"Crossref","is-referenced-by-count":11,"title":["Chip test pattern reordering method using adaptive test to reduce cost for testing of ICs"],"prefix":"10.1587","volume":"18","author":[{"given":"Tai","family":"Song","sequence":"first","affiliation":[{"name":"School of Electronic Science and Applied Physics, Hefei University of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Huaguo","family":"Liang","sequence":"additional","affiliation":[{"name":"School of Electronic Science and Applied Physics, Hefei University of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhengfeng","family":"Huang","sequence":"additional","affiliation":[{"name":"School of Electronic Science and Applied Physics, Hefei University of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tianming","family":"Ni","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, Anhui Polytechnic University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ying","family":"Sun","sequence":"additional","affiliation":[{"name":"Department of Computer Science and Technology, Pingdingshan Polytechnic college"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","unstructured":"[1] M.B. Alawieh, <i>et al.<\/i>: \u201cWafer map defect patterns classification using deep selective learning,\u201d 2020 57th ACM\/ESDA\/IEEE Design Automation Conference (DAC) (2020) (DOI: 10.1109\/dac18072.2020.9218580)."},{"key":"2","unstructured":"[2] T. Song, <i>et al.<\/i>: \u201cNovel application of deep learning for adaptive testing based on long short-term memory,\u201d 2019 IEEE 37th VTS (2019) (DOI: 10.1109\/vts.2019.8758628)."},{"key":"3","unstructured":"[3] H.-G. Stratigopoulos and C. Streitwieser: \u201cAdaptive test with test escape estimation for mixed-signal ICs,\u201d IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. <b>37<\/b> (2018) 2125 (DOI: 10.1109\/TCAD.2017.2783302)."},{"key":"4","unstructured":"[4] Semiconductor Industry Association: \u201cInternational roadmap for devices and system (IRDS),\u201d (2020)."},{"key":"5","unstructured":"[5] T. Song, <i>et al.<\/i>: \u201cPattern reorder for test cost reduction through improved SVMRANK algorithm,\u201d IEEE Access <b>8<\/b> (2020) 147965 (DOI: 10.1109\/access.2020.3016039)."},{"key":"6","unstructured":"[6] S.C. Ma, <i>et al.<\/i>: \u201cAn experimental chip to evaluate test techniques experiment results,\u201d Proc. Intl. Test Conf. (1995) 663 (DOI: 10.1109\/test.1995.529895)."},{"key":"7","unstructured":"[7] K.Y. Cho, <i>et al.<\/i>: \u201cGate exhaustive testing,\u201d Proc. Intl. Test Conf. (2005) 1 (DOI: 10.1109\/test.2005.1584040)."},{"key":"8","unstructured":"[8] F.-F. Ferhani, <i>et al.<\/i>: \u201cHow many test patterns are useless?,\u201d Proc. VLSI Test Symp. (2008) 23 (DOI: 10.1109\/vts.2008.27)."},{"key":"9","unstructured":"[9] S. Gupta, \u201cAdaptive online testing for efficient hard fault detection,\u201d 2009 IEEE International Conference on Computer Design (2009) 343 (DOI: 10.1109\/iccd.2009.5413132)."},{"key":"10","unstructured":"[10] P. Maxwell, \u201cAdaptive test directions,\u201d 2010 15th IEEE European Test Symposium (2010) 12 (DOI: 10.1109\/etsym.2010.5512789)."},{"key":"11","unstructured":"[11] A.D. Singh and C.M. Krishna: \u201cOn optimizing VLSI testing for product quality using die-yield prediction,\u201d IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. <b>12<\/b> (1993) 695 (DOI: 10.1109\/43.277614)."},{"key":"12","unstructured":"[12] P. Maxwell, \u201cAdaptive testing: dealing with process variability,\u201d IEEE Design Test Comput. <b>28<\/b> (2011) 41 (DOI: 10.1109\/mdt.2011.118)."},{"key":"13","unstructured":"[13] F. Hapke and P. Maxwell: \u201cTotal critical area based testing,\u201d 2018 IEEE ITC (2018) 1 (DOI: 10.1109\/TEST.2018.8624825)."},{"key":"14","unstructured":"[14] R. Pan, <i>et al.<\/i>: \u201cBlack-box test-coverage analysis and test-cost reduction based on a Bayesian network model,\u201d 2019 IEEE 37th VLSI Test Symposium (VTS) (2019) 1 (DOI: 10.1109\/vts.2019.8758639)."},{"key":"15","unstructured":"[15] R. Pan, <i>et al.<\/i>: \u201cBlack-box test-cost reduction based on Bayesian network models,\u201d IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. (DOI: 10.1109\/TCAD.2020.2994257)."},{"key":"16","unstructured":"[16] M. Shintani, <i>et al.<\/i>: \u201cA variability-aware adaptive test flow for test quality improvement,\u201d IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. <b>33<\/b> (2014) 1056 (DOI: 10.1109\/tcad.2014.2305835)."},{"key":"17","unstructured":"[17] M. Grady, <i>et al.<\/i>: \u201cAdaptive testing - cost reduction through test pattern sampling,\u201d 2013 IEEE International Test Conference (ITC) (2013) 1 (DOI: 10.1109\/test.2013.6651891)."},{"key":"18","unstructured":"[18] B. Xiao, <i>et al.<\/i>: \u201cNovel applications of deep learning hidden features for adaptive testing,\u201d 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC) (2016) 743 (DOI: 10.1109\/aspdac.2016.7428100)."},{"key":"19","unstructured":"[19] M. Liu, <i>et al.<\/i>: \u201cFine-grained adaptive testing based on quality prediction,\u201d 2018 IEEE ITC (2018) (DOI: 10.1109\/test.2018.8624891)."},{"key":"20","unstructured":"[20] M. Agrawal and K. Chakrabarty: \u201cTest-cost modeling and optimal test-flow selection of 3-D-stacked ICs,\u201d IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. <b>34<\/b> (2015) 1523 (DOI: 10.1109\/tcad.2015.2419227)."},{"key":"21","unstructured":"[21] K.-L. Wang, <i>et al.<\/i>: \u201cTest cost reduction methodology for InFO wafer-level chip-scale package,\u201d IEEE Design Test <b>34<\/b> (2017) 50 (DOI: 10.1109\/mdat.2016.2562060)."},{"key":"22","unstructured":"[22] S. Deyati, <i>et al.<\/i>: \u201cAdaptive testing of analog\/RF circuits using hardware extracted FSM models,\u201d 2016 IEEE 34th VLSI Test Symposium (VTS) (2016) 1 (DOI: 10.1109\/vts.2016.7477283)."},{"key":"23","unstructured":"[23] D. Zhao and S. Upadhyaya: \u201cDynamically partitioned test scheduling with adaptive TAM configuration for power-constrained SoC testing,\u201d IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. <b>24<\/b> (2005) 956 (DOI: 10.1109\/tcad.2005.847893)."},{"key":"24","doi-asserted-by":"publisher","unstructured":"[24] W. Zhan and Z. Shao: \u201cTest patterns reordering method based on gamma distribution,\u201d Integration <b>72<\/b> (2020) 66 (DOI: 10.1016\/j.vlsi.2019.12.008)","DOI":"10.1016\/j.vlsi.2019.12.008"},{"key":"25","unstructured":"[25] R. Tibshirani: \u201cRegression shrinkage and selection via the lasso,\u201d Journal of the Royal Statistical Society B <b>58<\/b> (1996) 267 (DOI: 10.1111\/j.2517-6161.1996.tb02080.x)."},{"key":"26","unstructured":"[26] A.E. Hoerl, and R.W. Kennard: \u201cRidge regression: biased estimation for nonorthogonal problems,\u201d Technometrics <b>12<\/b> (1970) 55 (DOI: 10.1080\/00401706.1970.10488634)."},{"key":"27","unstructured":"[27] H. Zou and T. Hastie: \u201cRegularization and variable selection via the elastic net,\u201d Journal of the Royal Statistical Society B <b>67<\/b> (2005) 301 (DOI: 10.1111\/j.1467-9868.2005.00503.x)."},{"key":"28","unstructured":"[28] T. Ni, <i>et al.<\/i>: \u201cArchitecture of cobweb-based redundant TSV for clustered faults,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>28<\/b> (2020) 1736 (DOI: 10.1109\/TVLSI.2020.2995094)."},{"key":"29","unstructured":"[29] T. Song, <i>et al.<\/i>: \u201cPattern reorder for test cost reduction through improved SVMRANK algorithm,\u201d IEEE Access <b>8<\/b> (2020) 147965 (DOI: 10.1109\/ACCESS.2020.3016039)."},{"key":"30","unstructured":"[30] C. Xue and R.D. Blanton: \u201cTest-set reordering for improving diagnosability,\u201d 2017 IEEE 35th VLSI Test Symposium (VTS) (2017) 1 (DOI: 10.1109\/VTS.2017.7928926)."}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/18\/2\/18_17.20200420\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,1,30]],"date-time":"2021-01-30T03:38:40Z","timestamp":1611977920000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/18\/2\/18_17.20200420\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,1,25]]},"references-count":30,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2021]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.17.20200420","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,1,25]]}}}