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Zhai, <i>et al.<\/i>: \u201cTheoretical and practical limits of dynamic voltage scaling,\u201d Proceedings 41st Design Automation Conference (2004) 1 (DOI: 10.1145\/996566.996798)."},{"key":"2","unstructured":"[2] H. Kaul, <i>et al.<\/i>: \u201cA 320mV 56\u00b5W 411GOPS\/watt ultra-low voltage motion estimation accelerator in 65nm CMOS,\u201d IEEE J. Solid-State Circuits <b>44<\/b> (2009) 107 (DOI: 10.1109\/JSSC.2008.2007164)."},{"key":"3","unstructured":"[3] R.G. Dreslinski, <i>et al.<\/i>: \u201cNear-threshold computing: reclaiming Moore\u2019s low through energy efficient integrated circuits,\u201d Proc. IEEE (2010) 253 (DOI: 10.1109\/JPROC.2009.2034764)."},{"key":"4","unstructured":"[4] H.-H. Hsieh, <i>et al.<\/i>: \u201cA 0.5-V 1.9-GHz low-power phase-locked loop in 0.18-\u00b5m CMOS,\u201d IEEE Symposium on VLSI Circuits (2007) 164 (DOI: 10.1109\/VLSIC.2007.4342699)."},{"key":"5","unstructured":"[5] T.-S. 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Shirane, <i>et al.<\/i>: \u201cA low voltage 0.8V RF receiver in 28nm CMOS for 5GHz WLAN,\u201d 43rd IEEE European Solid-State Circuits Conference (ESSCIRC) (2017) 328 (DOI: 10.1109\/ESSCIRC.2017.8094592)."},{"key":"10","unstructured":"[10] N. Joram, <i>et al.<\/i>: \u201cHigh swing PLL charge pump with current mismatch reduction,\u201d Electronics Letters <b>50<\/b> (2014) 661 (DOI: 10.1049\/el.2014.0804)."},{"key":"11","unstructured":"[11] R.R. Manikandan and B. Amrutur: \u201cA zero charge-pump mismatch current tracking loop for reference spur reduction in PLLs,\u201d Microelectronics J. <b>46<\/b> (2015) 422 (DOI: 10.1016\/j.mejo.2015.03.004)."},{"key":"12","unstructured":"[12] P. Qin, <i>et al.<\/i>: \u201cA fast and efficient automatic frequency calibration technique for 10 GHz PLLs,\u201d IEICE Electron. Express <b>11<\/b> (2014) 20140845 (DOI: 10.1587\/elex.11.20140845)."},{"key":"13","unstructured":"[13] Z. Zhang, <i>et al.<\/i>: \u201cSource-switched charge pump with reverse leakage compensation technique for spur reduction of wideband PLL,\u201d Electronics Letters <b>52<\/b> (2016) 1211 (DOI: 10.1049\/el.2016.1036)."},{"key":"14","unstructured":"[14] M. Jalalifar and G.-S. Byun: \u201cNear-threshold charge pump circuit using dual feedback loop,\u201d Electronics Letters <b>49<\/b> (2013) 1436 (DOI: 10.1049\/el.2013.1304)."},{"key":"15","unstructured":"[15] A. Paidimarri, <i>et al.<\/i>: \u201cA 0.68V 0.68mW 2.4GHz PLL for ultra-low power RF systems,\u201d IEEE Radio Frequency Integrated Circuits Symposium (RFIC) (2015) 397 (DOI: 10.1109\/RFIC.2015.7337789)."},{"key":"16","unstructured":"[16] N. Xi: \u201cA low reference spur phase-locked loop realized with dynamic current injection charge pump,\u201d IEICE Electron. Express <b>16<\/b> (2019) 20190095 (DOI: 10.1587\/elex.16.20190095)."},{"key":"17","unstructured":"[17] D. Mandal, <i>et al.<\/i>: \u201cPrediction of reference spur in frequency synthesizers,\u201d IET Circuits Dev. Syst. <b>9<\/b> (2015) 131 (DOI: 10.1049\/iet-cds.2014.0019)."},{"key":"18","unstructured":"[18] S.-W. Hsiao, <i>et al.<\/i>: \u201cPhase-locked loop design with SPO detection and charge pump trimming for reference spur suppression,\u201d IEEE 32nd VLSI Test Symposium (2014) (DOI: 10.1109\/VTS.2014.6818785)."},{"key":"19","unstructured":"[19] D. Biswas and T.K. Bhattacharyya: \u201cCharge pump with reduced current mismatch for reference spur minimization in PLLs,\u201d Analog Integr. Circuits Signal Process. <b>95<\/b> (2018) 209 (DOI: 10.1007\/s10470-018-1163-z)."},{"key":"20","unstructured":"[20] M.M. Elsayed, <i>et al.<\/i>: \u201cA spur-frequency-boosting PLL with a -74dBc reference-spur suppression in 90nm digital CMOS,\u201d IEEE J. Solid-State Circuits <b>48<\/b> (2013) 2104 (DOI: 10.1109\/JSSC.2013.2266865)."},{"key":"21","unstructured":"[21] D. Park, <i>et al.<\/i>: \u201cA 14.2 mW 2.55-to-3 GHz cascaded PLL with reference injection and 800 MHz delta-sigma modulator in 0.13-\u00b5m CMOS,\u201d IEEE J. Solid-State Circuits <b>47<\/b> (2012) 2989 (DOI: 10.1109\/JSSC.2012.2217856)."},{"key":"22","unstructured":"[22] D. Zhong, <i>et al.<\/i>: \u201cA perfectly current matched charge pump with wide dynamic range for ultra-low voltage applications,\u201d IEICE Electron. Express <b>11<\/b> (2014) 20140993 (DOI: 10.1587\/elex.11.20140993)."},{"key":"23","unstructured":"[23] C. Hangmann, <i>et al.<\/i>: \u201cStability analysis of a charge pump phase-locked loop using autonomous difference equations,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>61<\/b> (2014) 2569 (DOI: 10.1109\/TCSI.2014.2333331)."},{"key":"24","unstructured":"[24] J. Choi, <i>et al.<\/i>: \u201cA spur suppression technique using an edge-interpolator for a charge-pump PLL,\u201d IEEE Trans. Very Large Scale Integr. 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