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Kim, <i>et al.<\/i>: \u201cDesign and analysis of a 12-b current-steering DAC in a 14-nm FinFET technology for 2G\/3G\/4G cellular applications,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>66<\/b> (2019) 3723 (DOI: 10.1109\/TCSI.2019.2913174)."},{"key":"2","unstructured":"[2] G. Engel, <i>et al.<\/i>: \u201cA 14b 3\/6 GHz current-steering RF DAC in 0.18 \u00b5m CMOS with 66 dB ACLR at 2.9 GHz,\u201d IEEE ISSCC Dig. Tech. Papers (2012) 458 (DOI: 10.1109\/ISSCC.2012.6177089)."},{"key":"3","unstructured":"[3] G.I. Radulov, <i>et al.<\/i>: \u201cA 28-nm CMOS 1 V 3.5 GS\/s 6-bit DAC with signal-independent delta-I noise DfT scheme,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>23<\/b> (2015) 44 (DOI: 10.1109\/TVLSI.2014.2298055)."},{"key":"4","unstructured":"[4] M.J.M. Pelgrom, <i>et al.<\/i>: \u201cMatching properties of MOS transistors,\u201d IEEE J. Solid-State Circuits <b>24<\/b> (1989) 1433 (DOI: 10.1109\/JSSC.1989.572629)."},{"key":"5","unstructured":"[5] M. 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Kuo: \u201cA 0.07-mm<sup>2<\/sup> 162-mW DAC achieving <i>&gt;<\/i>65 dBc SFDR and <i>&lt;<\/i> -70 dBc IM3 at 10 GS\/s with output impedance compensation and concentric parallelogram routing,\u201d IEEE J. Solid-State Circuits <b>55<\/b> (2020) 2478 (DOI: 10.1109\/JSSC.2020.2993672)."},{"key":"21","unstructured":"[21] C.-H. Lin, <i>et al.<\/i>: \u201cA 12 bit 2.9 GS\/s DAC with IM3 \u226a -60 dBc beyond 1 GHz in 65 nm CMOS,\u201d IEEE J. Solid-State Circuits <b>44<\/b> (2009) 3285 (DOI: 10.1109\/JSSC.2009.2032624)."},{"key":"22","unstructured":"[22] P. Palmers and M.S.J. Steyaert: \u201cA 10-bit 1.6-GS\/s 27-mW current-steering D\/A converter with 550-MHz 54-dB SFDR bandwidth in 130-nm CMOS,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>57<\/b> (2010) 2870 (DOI: 10.1109\/TCSI.2010.2052491)."},{"key":"23","unstructured":"[23] A. Van den Bosch, <i>et al.<\/i>: \u201cA 10-bit 1-GSample\/s Nyquist current-steering CMOS D\/A converter,\u201d IEEE J. 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Li, <i>et al.<\/i>: \u201cA 14 Bit 500 MS\/s CMOS DAC using complementary switched current sources and time-relaxed interleaving DRRZ,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>61<\/b> (2014) 2337 (DOI: 10.1109\/TCSI.2014.2332248)."},{"key":"28","unstructured":"[28] W.-T. Lin, <i>et al.<\/i>: \u201cA 12-bit 40 nm DAC achieving SFDR <i>&gt;<\/i> 70 dB at 1.6 GS\/s and IMD <i>&lt;<\/i> -61dB at 2.8 GS\/s with DEMDRZ technique,\u201d IEEE J. Solid-State Circuits <b>49<\/b> (2014) 708 (DOI: 10.1109\/JSSC.2014.2301769)."},{"key":"29","unstructured":"[29] M.-H. Shen, <i>et al.<\/i>: \u201cRandom swapping dynamic element matching technique for glitch energy minimization in current-steering DAC,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>57<\/b> (2010) 369 (DOI: 10.1109\/TCSII.2010.2043400)."},{"key":"30","unstructured":"[30] F.-T. Chou and C.-C. Hung: \u201cGlitch energy reduction and SFDR enhancement techniques for low-power binary-weighted current-steering DAC,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>24<\/b> (2016) 2407 (DOI: 10.1109\/TVLSI.2015.2503727)."},{"key":"31","unstructured":"[31] R. Adams and K. Nguyen: U. S. Patent 6061010 (2000)."},{"key":"32","unstructured":"[32] S. Park, <i>et al.<\/i>: \u201cA digital-to-analog converter based on differential-quad switching,\u201d IEEE J. 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