{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,28]],"date-time":"2026-02-28T14:30:50Z","timestamp":1772289050254,"version":"3.50.1"},"reference-count":35,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"10","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2021,5,25]]},"DOI":"10.1587\/elex.18.20210136","type":"journal-article","created":{"date-parts":[[2021,4,13]],"date-time":"2021-04-13T22:11:54Z","timestamp":1618351914000},"page":"20210136-20210136","source":"Crossref","is-referenced-by-count":2,"title":["A 92 fs&lt;sub&gt;rms&lt;\/sub&gt; jitter frequency synthesizer based on a multicore class-C voltage-controlled oscillator with digital automatic amplitude control"],"prefix":"10.1587","volume":"18","author":[{"given":"Jiahao","family":"Chen","sequence":"first","affiliation":[{"name":"School of Aeronautics and Astronautics, Zhejiang University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Haoming","family":"Li","sequence":"additional","affiliation":[{"name":"School of Aeronautics and Astronautics, Zhejiang University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tengjia","family":"Wang","sequence":"additional","affiliation":[{"name":"School of Aeronautics and Astronautics, Zhejiang University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhiyu","family":"Wang","sequence":"additional","affiliation":[{"name":"School of Aeronautics and Astronautics, Zhejiang University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hua","family":"Chen","sequence":"additional","affiliation":[{"name":"School of Aeronautics and Astronautics, Zhejiang University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jiarui","family":"Liu","sequence":"additional","affiliation":[{"name":"School of Aeronautics and Astronautics, Zhejiang University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Faxin","family":"Yu","sequence":"additional","affiliation":[{"name":"School of Aeronautics and Astronautics, Zhejiang University"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] C. Erdmann, <i>et al.<\/i>: \u201c16.3 A 330mW 14b 6.8GS\/s dual-mode RF DAC in 16nm FinFET achieving -70.8dBc ACPR in a 20MHz channel at 5.2GHz,\u201d ISSCC Dig. Tech. Papers (2017) 280 (DOI: 10.1109\/ISSCC.2017.7870370).","DOI":"10.1109\/ISSCC.2017.7870370"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] S. Devarajan, <i>et al.<\/i>: \u201cA 12-b 10-GS\/s interleaved pipeline ADC in 28-nm CMOS technology,\u201d IEEE J. Solid-State Circuits <b>52<\/b> (2017) 3204 (DOI: 10.1109\/JSSC.2017.2747758).","DOI":"10.1109\/JSSC.2017.2747758"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] E. Groen <i>et al.<\/i>: \u201cA 10-to-112Gb\/s DSP-DAC-based transmitter with 1.2 <i>V<\/i><sub>ppd<\/sub> output swing in 7nm FinFET,\u201d ISSCC Dig. Tech. Papers (2020) 120 (DOI: 10.1109\/ISSCC19947.2020.9063130).","DOI":"10.1109\/ISSCC19947.2020.9063130"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] J. Im <i>et al.<\/i>: \u201cA 112 Gb\/s PAM-4 long-reach wireline transceiver using a 36-way time-interleaved SAR-ADC and inverter-based RX analog frontend in 7 nm FinFET,\u201d IEEE J. Solid-State Circuits <b>56<\/b> (2020) 7 (DOI: 10.1109\/JSSC.2020.3024261).","DOI":"10.1109\/ISSCC19947.2020.9063081"},{"key":"5","unstructured":"[5] X. Wang, <i>et al.<\/i>: \u201cKey factors analysis and design optimization of RF direct sampling receiver,\u201d IEEE ICCT (2018) 30 (DOI: 10.1109\/ICCT.2018.8600078)."},{"key":"6","unstructured":"[6] C.-M. Lai, <i>et al.<\/i>: \u201cA scalable direct-sampling broadband radar receiver supporting simultaneous digital multibeam array in 65nm CMOS,\u201d ISSCC Dig. Tech. Papers (2013) 242 (DOI: 10.1109\/ISSCC.2013.6487718)."},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] B. Razavi: \u201cJitter-power trade-offs in PLLs,\u201d IEEE Trans. Circuits and Syst. I, Reg. Papers <b>68<\/b> (2021) 1381 (DOI: 10.1109\/TCSI.2021.3057580).","DOI":"10.1109\/TCSI.2021.3057580"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] A. Hu, <i>et al.<\/i>: \u201cA 0.045- to 2.5-GHz frequency synthesizer with TDC-based AFC and phase switching multi-modulus divider,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>67<\/b> (2020) 4470 (DOI: 10.1109\/TCSI.2020.2997598).","DOI":"10.1109\/TCSI.2020.2997598"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] B. Sadhu, <i>et al.<\/i>: \u201cA capacitance boosted full-octave LC VCO based 0.7 to 24 GHz fractional-N synthesizer,\u201d IEEE RFIC (2015) 111 (DOI: 10.1109\/RFIC.2015.7337717).","DOI":"10.1109\/RFIC.2015.7337717"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] A. Elkholy, <i>et al.<\/i>: \u201cA 2.0-5.5 GHz wide bandwidth ring-based digital fractional-N PLL with extended range multi-modulus divider,\u201d IEEE J. Solid-State Circuits <b>51<\/b> (2016) 1771 (DOI: 10.1109\/JSSC.2016.2557807).","DOI":"10.1109\/JSSC.2016.2557807"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] W. Zou, <i>et al.<\/i>: \u201cA wideband low-jitter PLL with an optimized Ring-VCO,\u201d IEICE Electron. Express <b>17<\/b> (2020) 3 (DOI: 10.1587\/elex.17.20190703).","DOI":"10.1587\/elex.17.20190703"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] J. Kim, <i>et al.<\/i>: \u201cA low phase noise multi-band LC VCO using a switched differential inductor,\u201d IEICE Electron. Express <b>15<\/b> (2018) 7 (DOI: 10.1587\/elex.15.20180155).","DOI":"10.1587\/elex.15.20180155"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] A. Zanchi, <i>et al.<\/i>: \u201cImpact of AAC design on phase noise performance of VCOs,\u201d IEEE Trans. Circuits and Syst. II, Analog Digit. Signal Process. <b>48<\/b> (2001) 537 (DOI: 10.1109\/82.943325).","DOI":"10.1109\/82.943325"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] Y. Zhang, <i>et al.<\/i>: \u201cNovel hybrid type automatic amplitude control loop VCO,\u201d IEEE ICECC (2011) 356 (DOI: 10.1109\/ICECC.2011.6066652).","DOI":"10.1109\/ICECC.2011.6066652"},{"key":"15","doi-asserted-by":"crossref","unstructured":"[15] X. Xu, <i>et al.<\/i>: \u201c2.4-GHz band low-voltage class-C PMOS VCO IC with amplitude feedback loop,\u201d APMC (2015) 1 (DOI: 10.1109\/APMC.2015.7413483).","DOI":"10.1109\/APMC.2015.7413483"},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] D. Yan, <i>et al.<\/i>: \u201cA 3.1-4.2 GHz automatic amplitude control loop VCO with constant <i>K<\/i><sub>vco<\/sub> and <i>&lt;<\/i>10mV amplitude variation,\u201d IEEE ISCAS (2016) 1654 (DOI: 10.1109\/ISCAS.2016.7538884).","DOI":"10.1109\/ISCAS.2016.7538884"},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] A. Mazzanti and P. Andreani: \u201cClass-C harmonic CMOS VCOs, with a general result on phase noise,\u201d IEEE J. Solid-State Circuits <b>43<\/b> (2008) 2716 (DOI: 10.1109\/JSSC.2008.2004867).","DOI":"10.1109\/JSSC.2008.2004867"},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] M. Tohidian, <i>et al.<\/i>: \u201cHigh-swing class-C VCO,\u201d ESSCIRC (2011) 495 (DOI: 10.1109\/ESSCIRC.2011.6045015).","DOI":"10.1109\/ESSCIRC.2011.6045015"},{"key":"19","doi-asserted-by":"crossref","unstructured":"[19] W. Deng, <i>et al.<\/i>: \u201cClass-C VCO with amplitude feedback loop for robust start-up and enhanced oscillation swing,\u201d IEEE J. Solid-State Circuits <b>48<\/b> (2013) 429 (DOI: 10.1109\/JSSC.2012.2227603).","DOI":"10.1109\/JSSC.2012.2227603"},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] A. Mazzanti and P. Andreani: \u201cA push-pull class-C CMOS VCO,\u201d IEEE J. Solid-State Circuits <b>48<\/b> (2013) 3 (DOI: 10.1109\/JSSC.2012.2230542).","DOI":"10.1109\/JSSC.2012.2230542"},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] M. Tian, <i>et al.<\/i>: \u201cDesign of Q-enhanced class-C VCO with robust start-up and high oscillation stability,\u201d IEICE Electron. Express <b>11<\/b> (2014) 22 (DOI: 10.1587\/elex.11.20140982).","DOI":"10.1587\/elex.11.20140982"},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] X. Gao, <i>et al.<\/i>: \u201cA wideband simplified transformer-based VCO with digital amplitude calibration,\u201d IEEE MWSCAS (2017) 787 (DOI: 10.1109\/MWSCAS.2017.8053041).","DOI":"10.1109\/MWSCAS.2017.8053041"},{"key":"23","doi-asserted-by":"crossref","unstructured":"[23] Z. Zhang, <i>et al.<\/i>: \u201cA digitally reconfigurable auto amplitude calibration method for wide tuning range VCO design,\u201d IEEE ICSICT (2010) 542 (DOI: 10.1109\/ICSICT.2010.5667344).","DOI":"10.1109\/ICSICT.2010.5667344"},{"key":"24","doi-asserted-by":"crossref","unstructured":"[24] S.A.-R. Ahmadi-Mehr, <i>et al.<\/i>: \u201cAnalysis and design of a multi-core oscillator for ultra-low phase noise,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>63<\/b> (2016) 529 (DOI: 10.1109\/TCSI.2016.2529218).","DOI":"10.1109\/TCSI.2016.2529218"},{"key":"25","doi-asserted-by":"crossref","unstructured":"[25] L. Iotti, <i>et al.<\/i>: \u201cInsights into phase-noise scaling in switch-coupled multi-core LC VCOs for E-band adaptive modulation links,\u201d IEEE J. Solid-State Circuits <b>52<\/b> (2017) 1703 (DOI: 10.1109\/JSSC.2017.2697442).","DOI":"10.1109\/JSSC.2017.2697442"},{"key":"26","doi-asserted-by":"crossref","unstructured":"[26] F. Padovan, <i>et al.<\/i>: \u201cA quad-core 15GHz BiCMOS VCO with -124dBc\/Hz phase noise at 1MHz offset, -189dBc\/Hz FOM, and robust to multimode concurrent oscillations,\u201d ISSCC Dig. Tech. Papers (2018) 376 (DOI: 10.1109\/ISSCC.2018.8310341).","DOI":"10.1109\/ISSCC.2018.8310341"},{"key":"27","doi-asserted-by":"crossref","unstructured":"[27] L. Fanori and P. Andreani: \u201cHighly efficient class-C CMOS VCOs, including a comparison with class-B VCOs,\u201d IEEE J. Solid-State Circuits <b>48<\/b> (2013) 1730 (DOI: 10.1109\/JSSC.2013.2253402).","DOI":"10.1109\/JSSC.2013.2253402"},{"key":"28","doi-asserted-by":"crossref","unstructured":"[28] A. Hajimiri and T.H. Lee: \u201cA general theory of phase noise in electrical oscillators,\u201d IEEE J. Solid-State Circuits <b>33<\/b> (1998) 179 (DOI: 10.1109\/4.658619).","DOI":"10.1109\/4.658619"},{"key":"29","doi-asserted-by":"crossref","unstructured":"[29] X. Liao and L. Liu: \u201cA low-voltage robust Class-C VCO with dual digital feedback loops,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>67<\/b> (2020) 2347 (DOI: 10.1109\/TCSII.2020.2977145).","DOI":"10.1109\/TCSII.2020.2977145"},{"key":"30","doi-asserted-by":"crossref","unstructured":"[30] D. Li, <i>et al.<\/i>: \u201cA 5-GHz LC VCO with digital AAC and AFBS for 2.4GHz ZigBee transceiver applications,\u201d Microelectronics Journal <b>46<\/b> (2015) 415 (DOI: 10.1016\/j.mejo.2015.03.017).","DOI":"10.1016\/j.mejo.2015.03.017"},{"key":"31","doi-asserted-by":"crossref","unstructured":"[31] H. Yoon, <i>et al.<\/i>: \u201cA wideband dual-mode LC VCO with a switchable gate-biased active core,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>61<\/b> (2014) 289 (DOI: 10.1109\/TCSII.2014.2305216).","DOI":"10.1109\/TCSII.2014.2305216"},{"key":"32","doi-asserted-by":"crossref","unstructured":"[32] P. Litmanen, <i>et al.<\/i>: \u201cA wide-band transmitter and low-noise PLL for a highly integrated 4T-4R-2F ZIF transceiver in 28nm,\u201d IEEE RFIC (2018) 132 (DOI: 10.1109\/RFIC.2018.8429034).","DOI":"10.1109\/RFIC.2018.8429034"},{"key":"33","doi-asserted-by":"crossref","unstructured":"[33] M. Raj, <i>et al.<\/i>: \u201cA 164fsrms 9-to-18GHz sampling phase detector based PLL with in-band noise suppression and robust frequency acquisition in 16nm FinFET,\u201d Symp. on VLSI Circuits (2017) 182 (DOI: 10.23919\/VLSIC.2017.8008474).","DOI":"10.23919\/VLSIC.2017.8008474"},{"key":"34","doi-asserted-by":"crossref","unstructured":"[34] V. Ravinuthula and S. Finocchiaro: \u201cA low power high performance PLL with temperature compensated VCO in 65nm CMOS,\u201d IEEE RFIC (2016) 31 (DOI: 10.1109\/RFIC.2016.7508243).","DOI":"10.1109\/RFIC.2016.7508243"},{"key":"35","doi-asserted-by":"crossref","unstructured":"[35] D. Turker, <i>et al.<\/i>: \u201cA 7.4-to-14GHz PLL with 54fsrms jitter in 16nm FinFET for integrated RF-data-converter SoCs,\u201d ISSCC Dig. Tech. Papers (2018) 378 (DOI: 10.1109\/ISSCC.2018.8310342).","DOI":"10.1109\/ISSCC.2018.8310342"}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/18\/10\/18_18.20210136\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,6,9]],"date-time":"2021-06-09T06:18:29Z","timestamp":1623219509000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/18\/10\/18_18.20210136\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,5,25]]},"references-count":35,"journal-issue":{"issue":"10","published-print":{"date-parts":[[2021]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.18.20210136","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,5,25]]}}}