{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,5]],"date-time":"2025-11-05T14:30:54Z","timestamp":1762353054357},"reference-count":30,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"11","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2021,6,10]]},"DOI":"10.1587\/elex.18.20210156","type":"journal-article","created":{"date-parts":[[2021,5,16]],"date-time":"2021-05-16T22:06:48Z","timestamp":1621202808000},"page":"20210156-20210156","source":"Crossref","is-referenced-by-count":7,"title":["A high-speed low-power SAR ADC in 40nm CMOS with combined energy-efficient techniques"],"prefix":"10.1587","volume":"18","author":[{"given":"Yujia","family":"Huang","sequence":"first","affiliation":[{"name":"Institute of RF and OE-ICs, Southeast University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Qiao","family":"Meng","sequence":"additional","affiliation":[{"name":"Institute of RF and OE-ICs, Southeast University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Fei","family":"Li","sequence":"additional","affiliation":[{"name":"Institute of RF and OE-ICs, Southeast University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jie","family":"Wu","sequence":"additional","affiliation":[{"name":"Institute of RF and OE-ICs, Southeast University"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] C.-K. Hsu and T.-C. Lee: \u201cA single-channel 10-b 400-MS\/s 8.7-mW pipeline ADC in a 90-nm technology,\u201d ASSCC (2015) 1 (DOI: 10.1109\/ASSCC.2015.7387465).","DOI":"10.1109\/ASSCC.2015.7387465"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] C.-S. Shin and G.-C. Ahn: \u201cA 10-bit 100-MS\/s dual-channel pipelined ADC using dynamic memory effect cancellation technique,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>58<\/b> (2011) 274 (DOI: 10.1109\/TCSII.2011.2149130).","DOI":"10.1109\/TCSII.2011.2149130"},{"key":"3","unstructured":"[3] H.-W. Chen, <i>et al.<\/i>: \u201cA 10b 320MS\/s self-calibrated pipeline ADC,\u201d ASSCC (2010) 1 (DOI: 10.1109\/ASSCC.2010.5716583)."},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] C. Yang, <i>et al.<\/i>: \u201cAn 85mW 14-bit 150MS\/s pipelined ADC with 71.3dB peak SNDR in 130nm CMOS,\u201d ASSCC (2013) 85 (DOI: 10.1109\/ASSCC.2013.6690988).","DOI":"10.1109\/ASSCC.2013.6690988"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] A. Nicholson, <i>et al.<\/i>: \u201cA 0.3mm2 10-b 100MS\/s pipelined ADC using Nauta structure op-amps in 180nm CMOS,\u201d ISCAS (2013) 1833 (DOI: 10.1109\/ISCAS.2013.6572222).","DOI":"10.1109\/ISCAS.2013.6572222"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] C.-C. Liu, <i>et al.<\/i>: \u201cA 10 bit 320 MS\/s low-cost SAR ADC for IEEE 802.11ac applications in 20 nm CMOS,\u201d IEEE J. Solid-State Circuits <b>50<\/b> (2015) 2645 (DOI: 10.1109\/JSSC.2015.2466475).","DOI":"10.1109\/JSSC.2015.2466475"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] Y.-H. Chung and M.-S. Chiang: \u201cA 12-bit synchronous-SAR ADC for IoT applications,\u201d ISCAS (2019) 1 (DOI: 10.1109\/ISCAS.2019.8702620).","DOI":"10.1109\/ISCAS.2019.8702620"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] D.-G. Xu, <i>et al.<\/i>: \u201cA 12-bit 100-MS\/s 83 dB SFDR SAR ADC with sampling switch linearity enhanced technique,\u201d IEICE Electron. Express <b>16<\/b> (2019) 20190007 (DOI: 10.1587\/elex.16.20190007).","DOI":"10.1587\/elex.16.20190007"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] K.-H. Chang and C.-C. Hsieh: \u201cA 12 bit 150 MS\/s 1.5 mW SAR ADC with adaptive radix DAC in 40 nm CMOS,\u201d ASSCC (2016) 157 (DOI: 10.1109\/ASSCC.2016.7844159).","DOI":"10.1109\/ASSCC.2016.7844159"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] C.-H. Lee, <i>et al.<\/i>: \u201cA 2.5-bit\/cycle 10-bit 160-MS\/s SAR ADC in 90-nm CMOS process,\u201d VLSI-DAT (2016) 1 (DOI: 10.1109\/VLSI-DAT.2016.7482525).","DOI":"10.1109\/VLSI-DAT.2016.7482525"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] W. Li, <i>et al.<\/i>: \u201cA 13-bit 160MS\/s pipelined subranging-SAR ADC with low-offset dynamic comparator,\u201d ASSCC (2017) 225 (DOI: 10.1109\/ASSCC.2017.8240257).","DOI":"10.1109\/ASSCC.2017.8240257"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] C. Wu, <i>et al.<\/i>: \u201cA 12-bit, 300-MS\/s single-channel pipelined-SAR ADC with an open-loop MDAC,\u201d IEEE J. Solid-State Circuits <b>54<\/b> (2019) 1446 (DOI: 10.1109\/JSSC.2018.2886327).","DOI":"10.1109\/JSSC.2018.2886327"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] H. Huang, <i>et al.<\/i>: \u201cA non-interleaved 12-b 330-MS\/s pipelined-SAR ADC with PVT-stabilized dynamic amplifier achieving sub-1-dB SNDR variation,\u201d IEEE J. Solid-State Circuits <b>52<\/b> (2017) 3235 (DOI: 10.1109\/JSSC.2017.2732731).","DOI":"10.1109\/JSSC.2017.2732731"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] J. Gao, <i>et al.<\/i>: \u201cCentral span switching structure for SAR ADC with improved linearity and reduced DAC power,\u201d IEICE Electron. Express <b>12<\/b> (2015) 20150047 (DOI: 10.1587\/elex.12.20150047).","DOI":"10.1587\/elex.12.20150047"},{"key":"15","doi-asserted-by":"crossref","unstructured":"[15] W. Gu, <i>et al.<\/i>: \u201cSwitch-back based on charge equalization switching technique for SAR ADC,\u201d IEICE Electron. Express <b>12<\/b> (2015) 20150036 (DOI: 10.1587\/elex.12.20150036).","DOI":"10.1587\/elex.12.20150036"},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] M. Shahmohammadi, <i>et al.<\/i>: \u201cEnergy and area-efficient tri-level switching procedure based on half of the reference voltage for SAR ADC,\u201d IEICE Electron. Express <b>9<\/b> (2012) 1397 (DOI: 10.1587\/elex.9.1397).","DOI":"10.1587\/elex.9.1397"},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] H. Wang, <i>et al.<\/i>: \u201cTri-level capacitor-splitting switching scheme with high energy-efficiency for SAR ADCs,\u201d IEICE Electron. Express <b>13<\/b> (2016) 20160645 (DOI: 10.1587\/elex.13.20160645).","DOI":"10.1587\/elex.13.20160645"},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] R. Ding, <i>et al.<\/i>: \u201cUltra-low energy switching scheme for SAR ADC,\u201d The Institute of Electronics, Information and Communication Engineers <b>12<\/b> (2015) 20150439 (DOI: 10.1587\/elex.12.20150439).","DOI":"10.1587\/elex.12.20150439"},{"key":"19","doi-asserted-by":"crossref","unstructured":"[19] C.-C. Liu, <i>et al.<\/i>: \u201cA 10-bit 50-MS\/s SAR ADC with a monotonic capacitor switching procedure,\u201d IEEE J. Solid-State Circuits <b>45<\/b> (2010) 731 (DOI: 10.1109\/JSSC.2010.2042254).","DOI":"10.1109\/JSSC.2010.2042254"},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] G.-Y. Huang, <i>et al.<\/i>: \u201c10-bit 30-MS\/s SAR ADC using a switchback switching method,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>21<\/b> (2013) 584 (DOI: 10.1109\/TVLSI.2012.2190117).","DOI":"10.1109\/TVLSI.2012.2190117"},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] B.P. Ginsburg and A.P. Chandrakasan: \u201c500-MS\/s 5-bit ADC in 65-nm CMOS with split capacitor array DAC,\u201d J. Solid-State Circuits <b>42<\/b> (2007) 739 (DOI: 10.1109\/JSSC.2007.892169).","DOI":"10.1109\/JSSC.2007.892169"},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] V. Giannini, <i>et al.<\/i>: \u201cAn 820uW 9b 40MS\/s noise-tolerant dynamic-SAR ADC in 90nm digital CMOS,\u201d ISSCC (2009) 238 (DOI: 10.1109\/ISSCC.2008.4523145).","DOI":"10.1109\/ISSCC.2008.4523145"},{"key":"23","doi-asserted-by":"crossref","unstructured":"[23] H. Fan, <i>et al.<\/i>: \u201cA 12-bit self-calibrating SAR ADC achieving a Nyquist 90.4-dB SFDR,\u201d Analog Integrated Circuits and Signal Processing <b>74<\/b> (2013) 239 (DOI: 10.1007\/s10470-012-9977-6).","DOI":"10.1007\/s10470-012-9977-6"},{"key":"24","doi-asserted-by":"crossref","unstructured":"[24] D. Xu, <i>et al.<\/i>: \u201cA system-level correction SAR ADC with noise-tolerant technique,\u201d Journal of Circuits, Systems and Computers <b>27<\/b> (2018) 1850202 (DOI: 10.1142\/S021812661850202X).","DOI":"10.1142\/S021812661850202X"},{"key":"25","doi-asserted-by":"crossref","unstructured":"[25] Y. Zhu, <i>et al.<\/i>: \u201cA 10-bit 100-MS\/s reference-free SAR ADC in 90 nm CMOS,\u201d Journal of Solid-State Circuits <b>45<\/b> (2010) 1111 (DOI: 10.1109\/JSSC.2010.2048498).","DOI":"10.1109\/JSSC.2010.2048498"},{"key":"26","doi-asserted-by":"crossref","unstructured":"[26] S. Liu, <i>et al.<\/i>: \u201cA 12-bit 10 MS\/s SAR ADC with high linearity and energy-efficient switching,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>63<\/b> 1616 (2016) (DOI: 10.1109\/TCSI.2016.2581177).","DOI":"10.1109\/TCSI.2016.2581177"},{"key":"27","unstructured":"[27] G. Huang, <i>et al.<\/i>: \u201cAnalysis and optimization of a SAR ADC with attenuation capacitor,\u201d MIPRO (2014) 68 (DOI: 10.1109\/MIPRO.2014.6859535)."},{"key":"28","unstructured":"[28] Y.-S. Hu, <i>et al.<\/i>: \u201cA 0.6V 6.4fJ\/conversion-step 10-bit 150MS\/s subranging SAR ADC in 40nm CMOS,\u201d ASSCC (2010) 81 (DOI: 10.1109\/ASSCC.2014.7008865)."},{"key":"29","unstructured":"[29] M. Miyahara, <i>et al.<\/i>: \u201cA low-noise self-calibrating dynamic comparator for high-speed ADCs,\u201d ASSCC (2008) 269 (DOI: 10.1109\/ASSCC.2008.4708780)."},{"key":"30","doi-asserted-by":"crossref","unstructured":"[30] D. Schinkel, <i>et al.<\/i>: \u201cA double-tail latch-type voltage sense amplifier with 18ps setup+hold time,\u201d ISSCC (2007) 314 (DOI: 10.1109\/ISSCC.2007.373420).","DOI":"10.1109\/ISSCC.2007.373420"}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/18\/11\/18_18.20210156\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,6,10]],"date-time":"2021-06-10T05:33:11Z","timestamp":1623303191000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/18\/11\/18_18.20210156\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,6,10]]},"references-count":30,"journal-issue":{"issue":"11","published-print":{"date-parts":[[2021]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.18.20210156","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,6,10]]}}}