{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,11,12]],"date-time":"2022-11-12T05:39:32Z","timestamp":1668231572459},"reference-count":30,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"19","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2021,10,10]]},"DOI":"10.1587\/elex.18.20210195","type":"journal-article","created":{"date-parts":[[2021,6,8]],"date-time":"2021-06-08T22:08:56Z","timestamp":1623190136000},"page":"20210195-20210195","source":"Crossref","is-referenced-by-count":1,"title":["Adaptive one-way SLC\/TLC mode conversion in high density SSDs"],"prefix":"10.1587","volume":"18","author":[{"given":"Mingwang","family":"Zhao","sequence":"first","affiliation":[{"name":"College of Computer and Information Science, Southwest University of China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhigang","family":"Cai","sequence":"additional","affiliation":[{"name":"College of Computer and Information Science, Southwest University of China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lihao","family":"Song","sequence":"additional","affiliation":[{"name":"College of Computer and Information Science, Southwest University of China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yuanquan","family":"Shi","sequence":"additional","affiliation":[{"name":"The College of Computer Science and Engineering, Huaihua University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Min","family":"Huang","sequence":"additional","affiliation":[{"name":"College of Computer and Information Science, Southwest University of China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] J. Liao, <i>et al.<\/i>: \u201cAdaptive wear-leveling in flash-based memory,\u201d IEEE Comput. Archit. Lett. <b>14<\/b> (2015) 1 (DOI: 10.1109\/lca.2014.2329871).","DOI":"10.1109\/LCA.2014.2329871"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] J. Li, <i>et al.<\/i>: \u201cPattern-based write scheduling and read balance-oriented wear-leveling for solid state drivers,\u201d MSST (2019) 126 (DOI: 10.1109\/msst.2019.00-10).","DOI":"10.1109\/MSST.2019.00-10"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] C. Matsui, <i>et al.<\/i>: \u201cDesign of hybrid SSDs with storage class memory and NAND flash memory,\u201d Proc. IEEE <b>105<\/b> (2017) 1812 (DOI: 10.1109\/jproc.2017.2716958).","DOI":"10.1109\/JPROC.2017.2716958"},{"key":"4","unstructured":"[4] Y. Cai, <i>et al.<\/i>: \u201cRead disturb errors in MLC NAND flash memory,\u201d CoRR (2018) abs\/1805.03283."},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] W. Lee, <i>et al.<\/i>: \u201cInterpage-based endurance-enhancing lower state encoding for MLC and TLC flash memory storages,\u201d TVLSI <b>27<\/b> (2019) 2033 (DOI: 10.1109\/tvlsi.2019.2912228).","DOI":"10.1109\/TVLSI.2019.2912228"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] J. Li, <i>et al.<\/i>: \u201cPatch-based data management for dual-copy buffers in RAID-enabled SSDs,\u201d TCAD <b>39<\/b> (2020) 3956 (DOI: 10.1109\/tcad.2020.3012252).","DOI":"10.1109\/TCAD.2020.3012252"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] M. Fukuchi, <i>et al.<\/i>: \u201cSystem performance comparison of 3D charge-trap TLC NAND flash and 2D floating-gate MLC NAND flash based SSDs,\u201d IEICE Trans. Electron. <b>103-C<\/b> (2020) 161 (DOI: 10.1587\/transele.2019cdp0005).","DOI":"10.1587\/transele.2019CDP0005"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] L. Yang, <i>et al.<\/i>: \u201cWord line interference based data recovery technique for 3D NAND flash,\u201d IEICE Electronic Express <b>15<\/b> (2018) 20180762 (DOI: 10.1587\/elex.15.20180762).","DOI":"10.1587\/elex.15.20180762"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] X. Shi, <i>et al.<\/i>: \u201cProgram error rate-based wear leveling for NAND flash memory,\u201d DATE (2018) 1241 (DOI: 10.23919\/date.2018.8342205).","DOI":"10.23919\/DATE.2018.8342205"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] Y. Arakawa, <i>et al.<\/i>: \u201cSilicon photonics for next generation system integration platform,\u201d IEEE Commun. Mag. <b>51<\/b> (2013) 72 (DOI: 10.1109\/mcom.2013.6476868).","DOI":"10.1109\/MCOM.2013.6476868"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] Y. Cai, <i>et al.<\/i>: \u201cError characterization, mitigation, and recovery in flash-memory-based solid-state drives,\u201d Proc. IEEE <b>105<\/b> (2017) 1666 (DOI: 10.1109\/jproc.2017.2713127).","DOI":"10.1109\/JPROC.2017.2713127"},{"key":"12","unstructured":"[12] G. Geoff: \u201cSamsung\u2019s 840 EVO solid-state drive reviewed TLC NAND with a shot of SLC cache,\u201d https:\/\/techreport.com\/review\/25122\/samsungs-840-evo-solid-state-drive-reviewed\/."},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] R. Cao, <i>et al.<\/i>: \u201cLoad prediction for data centers based on database service,\u201d COMPSAC, (2018) 728 (DOI: 10.1109\/compsac.2018.00109).","DOI":"10.1109\/COMPSAC.2018.00109"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] C. Gao, <i>et al.<\/i>: \u201cConstructing large, durable and fast SSD system via reprogramming 3D TLC flash memory,\u201d MICRO (2019) 493 (DOI: 10.1145\/3352460.3358323).","DOI":"10.1145\/3352460.3358323"},{"key":"15","doi-asserted-by":"crossref","unstructured":"[15] S. Li, <i>et al.<\/i>: \u201cAccelerating garbage collection for 3D MLC flash memory with SLC blocks,\u201d ICCAD (2019) 1 (DOI: 10.1109\/iccad45719.2019.8942097).","DOI":"10.1109\/ICCAD45719.2019.8942097"},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] D. Liu, <i>et al.<\/i>: \u201cA workload-aware flash translation layer enhancing performance and lifespan of TLC\/SLC dual-mode flash memory in embedded systems,\u201d MICPRO <b>52<\/b> (2017) 343 (DOI: 10.1016\/j.micpro.2016.12.009).","DOI":"10.1016\/j.micpro.2016.12.009"},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] X. Jimenez, <i>et al.<\/i>: \u201cSoftware controlled cell bit-density to improve NAND flash lifetime,\u201d DAC (2012) 229 (DOI: 10.1145\/2228360.2228404).","DOI":"10.1145\/2228360.2228404"},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] C.-W. Chang, <i>et al.<\/i>: \u201cExploiting write heterogeneity of morphable MLC\/SLC SSDs in datacenters with service-level objectives,\u201d IEEE Trans. Computers <b>66<\/b> (2017) 1457 (DOI: 10.1109\/tc.2017.2677425).","DOI":"10.1109\/TC.2017.2677425"},{"key":"19","unstructured":"[19] G. Marotta, <i>et al.<\/i>: \u201cU.S. Patent USOO8407400B2 (2013)."},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] L. Yao, <i>et al.<\/i>: \u201cTLC-FTL: workload-aware flash translation layer for TLC\/SLC dual-mode flash memory in embedded systems,\u201d HPCC (2015) 831 (DOI: 10.1109\/hpcc-css-icess.2015.263).","DOI":"10.1109\/HPCC-CSS-ICESS.2015.263"},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] C. Loboz: \u201cCloud resource usage - heavy tailed distributions invalidating traditional capacity planning models,\u201d J. Grid Comput. <b>10<\/b> (2012) 85 (DOI: 10.1007\/s10723-012-9211-x).","DOI":"10.1007\/s10723-012-9211-x"},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] A. Klimovic, <i>et al.<\/i>: \u201cFlash storage disaggregation,\u201d EuroSys (2016) 29: 1 (DOI: 10.1145\/2901318.2901337).","DOI":"10.1145\/2901318.2901337"},{"key":"23","unstructured":"[23] R. Hal, <i>et al.<\/i>: <i>Intermediate Microeconomics a Modern Approach<\/i> (W.W. Norton, 2019) 9th ed."},{"key":"24","doi-asserted-by":"crossref","unstructured":"[24] S. Wang, <i>et al.<\/i>: \u201cAdaptive optimal parameter estimation and control of servo mechanisms: theory and experiments,\u201d IEEE Trans. Ind. Electron. <b>68<\/b> (2021) 598 (DOI: 10.1109\/tie.2019.2962445).","DOI":"10.1109\/TIE.2019.2962445"},{"key":"25","doi-asserted-by":"crossref","unstructured":"[25] Y. Hu, <i>et al.<\/i>: \u201cPerformance impact and interplay of SSD parallelism through advanced commands, allocation strategy and data granularity,\u201d ICS (2011) 96 (DOI: 10.1145\/1995896.1995912).","DOI":"10.1145\/1995896.1995912"},{"key":"26","doi-asserted-by":"crossref","unstructured":"[26] M. Fukuchi, <i>et al.<\/i>: \u201c20% System-performance gain of 3D charge-trap TLC NAND flash over 2D floating-gate MLC NAND flash for SCM\/NAND flash hybrid SSD,\u201d ISCAS (2018) 1 (DOI: 10.1109\/iscas.2018.8351309).","DOI":"10.1109\/ISCAS.2018.8351309"},{"key":"27","doi-asserted-by":"crossref","unstructured":"[27] J. Li, <i>et al.<\/i>: \u201cMitigating negative impacts of read disturb in SSDs,\u201d ToDAES <b>26<\/b> (2020) 1 (DOI: 10.1145\/3410332).","DOI":"10.1145\/3410332"},{"key":"28","doi-asserted-by":"crossref","unstructured":"[28] D. Narayanan, <i>et al.<\/i>: \u201cWrite off-loading: practical power management for enterprise storage,\u201d TOS <b>4<\/b> (2008) 10: 1 (DOI: 10.1145\/1416944.1416949).","DOI":"10.1145\/1416944.1416949"},{"key":"29","doi-asserted-by":"crossref","unstructured":"[29] C. Lee, <i>et al.<\/i>: \u201cUnderstanding storage traffic characteristics on enterprise virtual desktop infrastructure,\u201d SYSTOR (2017) 13: 1 (DOI: 10.1145\/3078468.3078479).","DOI":"10.1145\/3078468.3078479"},{"key":"30","doi-asserted-by":"crossref","unstructured":"[30] K. Ha, <i>et al.<\/i>: \u201cAn integrated approach for managing read disturbs in high-density NAND flash memory,\u201d TCAD <b>35<\/b> (2016) 1079 (DOI: 10.1109\/tcad.2015.2504868).","DOI":"10.1109\/TCAD.2015.2504868"}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/18\/19\/18_18.20210195\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,16]],"date-time":"2021-10-16T04:08:09Z","timestamp":1634357289000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/18\/19\/18_18.20210195\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,10,10]]},"references-count":30,"journal-issue":{"issue":"19","published-print":{"date-parts":[[2021]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.18.20210195","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,10,10]]},"article-number":"18.20210195"}}