{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,5,9]],"date-time":"2024-05-09T00:15:49Z","timestamp":1715213749166},"reference-count":32,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"24","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2021,12,25]]},"DOI":"10.1587\/elex.18.20210451","type":"journal-article","created":{"date-parts":[[2021,11,14]],"date-time":"2021-11-14T22:08:16Z","timestamp":1636927696000},"page":"20210451-20210451","source":"Crossref","is-referenced-by-count":0,"title":["Time multiplexed LBIST for in-field testing of automotive AI accelerators"],"prefix":"10.1587","volume":"18","author":[{"given":"Umair Saeed","family":"Solangi","sequence":"first","affiliation":[{"name":"Dept. of Computer Science &amp; Engineering, Hanyang University"},{"name":"Dept. of Electronic Engineering, Quaid-e-Awam University of Engineering Science &amp; Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Muhammad","family":"Ibtesam","sequence":"additional","affiliation":[{"name":"Dept. of Computer Science &amp; Engineering, Hanyang University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sungju","family":"Park","sequence":"additional","affiliation":[{"name":"Dept. of Computer Science &amp; Engineering, Hanyang University"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","unstructured":"[1] P.J. Bannon: U.S. Patent 0 026 078 A1 (2017)."},{"key":"2","unstructured":"[2] N.P. Jouppi, <i>et al.<\/i>: \u201cIn-datacenter performance analysis of a tensor processing unit,\u201d 2017 ACM\/IEEE 44th Annual International Symposium on Computer Architecture (ISCA), (2017) 1 (DOI: 10.1145\/3079856.3080246)."},{"key":"3","unstructured":"[3] J. Ross, <i>et al<\/i>.: U.S. Patent 9747546 B2 (2015)."},{"key":"4","unstructured":"[4] J. Ross and A. Phelps: U.S. Patent 9697463 B2 (2015)."},{"key":"5","unstructured":"[5] J. Ross: U.S. Patent 9805304 B2 (2015)."},{"key":"6","unstructured":"[6] J. Ross and G. Thorson: U.S. Patent 9747548 B2 (2015)."},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] Y. Chen, <i>et al.<\/i>: \u201cEyeriss v2: a flexible accelerator for emerging deep neural networks on mobile devices,\u201d IEEE J. Emerg. Sel. Topics Circuits Syst. <b>9<\/b>, (2019) 292 (DOI: 10.1109\/JETCAS.2019.2910232).","DOI":"10.1109\/JETCAS.2019.2910232"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] T. Chen, <i>et al.<\/i>: \u201cDianNao: a small-footprint high-throughput accelerator for ubiquitous machine-learning,\u201d SIGARCH Comput. Archit. News <b>42<\/b> (2014) 269 (DOI: 10.1145\/2654822.2541967).","DOI":"10.1145\/2654822.2541967"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] L. Cavigelli, <i>et al.<\/i>: \u201cOrigami: a convolutional network accelerator\u201d, Proc. 25th Ed. Great Lakes Symp. VLSI(2015) 199 (DOI: 10.1145\/2742060.2743766).","DOI":"10.1145\/2742060.2743766"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] J.J. Zhang, <i>et al.<\/i>: \u201cAnalyzing and mitigating the impact of permanent faults on a systolic array based neural network accelerator,\u201d Proc. IEEE 36th VLSI Test Symp. (VTS) (2018) 1 (DOI: 10.1109\/VTS.2018.8368656).","DOI":"10.1109\/VTS.2018.8368656"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] S. Kundu, <i>et al.<\/i>: \u201cToward functional safety of systolic array-based deep learning hardware accelerators,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>29<\/b> (2021) 485 (DOI: 10.1109\/TVLSI.2020.3048829).","DOI":"10.1109\/TVLSI.2020.3048829"},{"key":"12","unstructured":"[12] C. Hobbs and P. Lee: \u201cUnderstanding ISO 26262 ASILs,\u201d Electron. Des. (2013) http:\/\/electronicdesign.com"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] S.R. Das: \u201cGetting errors to catch themselves--self-testing of VLSI circuits with built-in hardware,\u201d IEEE Trans. Instrum. Meas. <b>54<\/b> (2005) 941 (DOI: 10.1109\/TIM.2005.847352).","DOI":"10.1109\/TIM.2005.847352"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] Y. Liu, <i>et al.<\/i>: \u201cDeterministic stellar BIST for in-system automotive test,\u201d IEEE Int. Test Conf. (ITC) (2018) 1 (DOI: 10.1109\/TEST.2018.8624872).","DOI":"10.1109\/TEST.2018.8624872"},{"key":"15","doi-asserted-by":"crossref","unstructured":"[15] W. Wang, <i>et al<\/i>.: \u201cLow power logic BIST with high test effectiveness,\u201d IEICE Electron. Express, <b>10<\/b> (2013) 1 (DOI: 10.1587\/elex.10.20130853).","DOI":"10.1587\/elex.10.20130853"},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] D. Gizopoulos, <i>et al.<\/i>: \u201cPower aware testing and test strategies for low power devices,\u201d Design Autom. and Test in Europe (2008) xliv (DOI: 10.1109\/DATE.2008.4484642).","DOI":"10.1109\/DATE.2008.4484642"},{"key":"17","unstructured":"[17] P. Girard, <i>et al.<\/i>: \u201cCircuit partitioning for low power BIST design with minimized peak power consumption,\u201d Proc. 8th Asian Test Symp. (ATS\u201999) (1999) 89 (DOI: 10.1109\/ATS.1999.810734)."},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] N. Mukherjee, <i>et al.<\/i>: \u201cTime and area optimized testing of automotive ICs,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>29<\/b> (2021) 76 (DOI: 10.1109\/TVLSI.2020.3025138).","DOI":"10.1109\/TVLSI.2020.3025138"},{"key":"19","doi-asserted-by":"crossref","unstructured":"[19] H. Ma, <i>et al.<\/i>: \u201cA case study of testing strategy for AI SoC,\u201d Proc. IEEE Int. Test Conf. Asia (ITC-Asia) (2019) 61 (DOI: 10.1109\/ITC-Asia.2019.00024).","DOI":"10.1109\/ITC-Asia.2019.00024"},{"key":"20","unstructured":"[20] R. Singhal: \u201cAI chip DFT techniques for aggressive time-to-market,\u201d Mentor, Siemens Bus., White Paper (2019)."},{"key":"21","unstructured":"[21] H.K. Lau, <i>et al.<\/i>: \u201cEnabling DFT and fast silicon bring-up for massive AI chip-case study\u201d, IEEE Int. Test Conf. (ITC) (2019)."},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] U.S. Solangi, <i>et al.<\/i>: \u201cTest architecture for systolic array of edge-based AI accelerator,\u201d IEEE Access <b>9<\/b> (2021) 96700 (DOI: 10.1109\/ACCESS.2021.3094741).","DOI":"10.1109\/ACCESS.2021.3094741"},{"key":"23","doi-asserted-by":"crossref","unstructured":"[23] M. Ibtesam, <i>et al.<\/i>: \u201cHighly efficient test architecture for low power AI accelerators,\u201d IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. (2021) (DOI: 10.1109\/TCAD.2021.3110739).","DOI":"10.1109\/TCAD.2021.3110739"},{"key":"24","doi-asserted-by":"crossref","unstructured":"[24] M. Ibtesam, <i>et al.<\/i>: \u201cReliable test architecture with test cost reduction for systolic based DNN accelerators,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs (2021) (DOI: 10.1109\/TCSII.2021.3108415).","DOI":"10.1109\/TCSII.2021.3108415"},{"key":"25","doi-asserted-by":"crossref","unstructured":"[25] M.A. Ansari, <i>et al.<\/i>: \u201cTime division multiplexing based test access for stacked ICs,\u201d Journal of Semiconductor Technology and Science <b>19<\/b> (2019) 87 (DOI: 10.5573\/JSTS.2019.19.1.087).","DOI":"10.5573\/JSTS.2019.19.1.087"},{"key":"26","doi-asserted-by":"crossref","unstructured":"[26] M.A. Ansari, <i>et al.<\/i>: \u201cTime-multiplexed 1687-network for test cost reduction,\u201d IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. <b>37<\/b> (2018) 1681 (DOI: 10.1109\/TCAD.2017.2766146).","DOI":"10.1109\/TCAD.2017.2766146"},{"key":"27","doi-asserted-by":"crossref","unstructured":"[27] M.A. Ansari, <i>et al<\/i>.: \u201cTime multiplexed test access architecture for stacked integrated circuits,\u201d IEICE Electron. Express <b>13<\/b> (2016) 1 (DOI: 10.1587\/elex.13.20160314).","DOI":"10.1587\/elex.13.20160314"},{"key":"28","unstructured":"[28] S. Wang and S.K. Gupta: \u201cDS-LFSR: a new BIST TPG for low heat dissipation,\u201d Proc. Int. Test Conf. (1997) 848 (DOI: 10.1109\/TEST.1997.639699)."},{"key":"29","unstructured":"[29] P. Girard, <i>et al.<\/i>: \u201cA modified clock scheme for a low power BIST test pattern generator,\u201d Proc. 19th IEEE VLSI Test Symp. (VTS) (2001) 306 (DOI: 10.1109\/VTS.2001.923454)."},{"key":"30","unstructured":"[30] Y. Bonhomme, <i>et al.<\/i>: \u201cA gated clock scheme for low power scan testing of logic ICs or embedded cores,\u201d Proc. 10th Asian Test Symp. (2001) 253 (DOI: 10.1109\/ATS.2001.990291)."},{"key":"31","doi-asserted-by":"crossref","unstructured":"[31] C.P. de Souza, <i>et al.<\/i>: \u201cA new architecture of test response analyzer based on the Berlekamp-Massey algorithm for BIST,\u201d IEEE Trans. Instrum. Meas. <b>59<\/b> (2010) 3168 (DOI: 10.1109\/TIM.2010.2047171).","DOI":"10.1109\/TIM.2010.2047171"},{"key":"32","doi-asserted-by":"crossref","unstructured":"[32] Y. Yu, <i>et al<\/i>.: \u201cEfficient concurrent BIST with comparator-based response analyzer,\u201d Proc. IEEE Int. Instrum. Meas. Technol. Conf. (I2MTC) (2013) 1115 (DOI: 10.1109\/I2MTC.2013.6555587).","DOI":"10.1109\/I2MTC.2013.6555587"}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/18\/24\/18_18.20210451\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,5,8]],"date-time":"2024-05-08T04:28:46Z","timestamp":1715142526000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/18\/24\/18_18.20210451\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,12,25]]},"references-count":32,"journal-issue":{"issue":"24","published-print":{"date-parts":[[2021]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.18.20210451","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,12,25]]},"article-number":"18.20210451"}}