{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,29]],"date-time":"2025-10-29T13:46:16Z","timestamp":1761745576303},"reference-count":30,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"1","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2022,1,10]]},"DOI":"10.1587\/elex.18.20210493","type":"journal-article","created":{"date-parts":[[2021,12,5]],"date-time":"2021-12-05T22:08:14Z","timestamp":1638742094000},"page":"20210493-20210493","source":"Crossref","is-referenced-by-count":3,"title":["Optimized fast data migration for hybrid DRAM\/STT-MRAM main memory"],"prefix":"10.1587","volume":"19","author":[{"given":"Chenji","family":"Liu","sequence":"first","affiliation":[{"name":"Institute of Microelectronics of Chinese Academy of Sciences"},{"name":"University of Chinese Academy of Sciences"},{"name":"Beijing Key Laboratory of Three-dimensional and Nanometer Integrated Circuit Design Automation Technology"}]},{"given":"Lan","family":"Chen","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of Chinese Academy of Sciences"},{"name":"University of Chinese Academy of Sciences"},{"name":"Beijing Key Laboratory of Three-dimensional and Nanometer Integrated Circuit Design Automation Technology"}]},{"given":"Xiaoran","family":"Hao","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of Chinese Academy of Sciences"},{"name":"Beijing Key Laboratory of Three-dimensional and Nanometer Integrated Circuit Design Automation Technology"}]},{"given":"Mao","family":"Ni","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of Chinese Academy of Sciences"},{"name":"Beijing Key Laboratory of Three-dimensional and Nanometer Integrated Circuit Design Automation Technology"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] S.W. 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Code Optim. <b>14<\/b> (2017) 1 (DOI: 10.1145\/3085572).","DOI":"10.1145\/3085572"}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/19\/1\/19_18.20210493\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,5,9]],"date-time":"2024-05-09T05:01:09Z","timestamp":1715230869000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/19\/1\/19_18.20210493\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,1,10]]},"references-count":30,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2022]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.18.20210493","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,1,10]]},"article-number":"18.20210493"}}