{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,30]],"date-time":"2022-04-30T05:41:38Z","timestamp":1651297298400},"reference-count":30,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"8","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2022,4,25]]},"DOI":"10.1587\/elex.19.20220009","type":"journal-article","created":{"date-parts":[[2022,3,27]],"date-time":"2022-03-27T22:09:13Z","timestamp":1648418953000},"page":"20220009-20220009","source":"Crossref","is-referenced-by-count":0,"title":["Two novel PSRR enhancement techniques for voltage reference of depletion NMOS"],"prefix":"10.1587","volume":"19","author":[{"given":"Boqi","family":"Song","sequence":"first","affiliation":[{"name":"Key Laboratory of Ministry of Education for Wide BandGap Semiconductor Materials and Devices, School of Microelectronics, Xidian University"}]},{"given":"Changchun","family":"Chai","sequence":"additional","affiliation":[{"name":"Key Laboratory of Ministry of Education for Wide BandGap Semiconductor Materials and Devices, School of Microelectronics, Xidian University"}]},{"given":"Fuxing","family":"Li","sequence":"additional","affiliation":[{"name":"Key Laboratory of Ministry of Education for Wide BandGap Semiconductor Materials and Devices, School of Microelectronics, Xidian University"}]},{"given":"Chanrong","family":"Jiang","sequence":"additional","affiliation":[{"name":"Key Laboratory of Ministry of Education for Wide BandGap Semiconductor Materials and Devices, School of Microelectronics, Xidian University"}]},{"given":"Yintang","family":"Yang","sequence":"additional","affiliation":[{"name":"Key Laboratory of Ministry of Education for Wide BandGap Semiconductor Materials and Devices, School of Microelectronics, Xidian University"}]}],"member":"532","reference":[{"key":"1","unstructured":"[1] P.E. Allen and D.R. Holberg: <i>CMOS Analog Circuits Design<\/i> (Oxford University Press, 2000) 2nd ed."},{"key":"2","unstructured":"[2] B. Razavi: <i>Design of Analog CMOS Integrated Circuits<\/i> (McGraw-Hill, New York, 2000)."},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] M. Chahardori, <i>et al<\/i>.: \u201cA sub 1V high PSRR CMOS bandgap voltage reference,\u201d Microelectronics Journal <b>42<\/b> (2011) 1057 (DOI: 10.1016\/j.mejo.2011.06.010).","DOI":"10.1016\/j.mejo.2011.06.010"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] J. Wu, <i>et al.<\/i>: \u201cA high PSRR CMOS voltage reference with 1.2V operation,\u201d Analog Integr. Circuits Signal Process <b>77<\/b> (2013) 79 (DOI: 10.1007\/s10470-013-0122-y).","DOI":"10.1007\/s10470-013-0122-y"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] Y.-B. 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He, <i>et al<\/i>.: \u201cA 0.5V 46.2ppm\/<sup>\u00b0<\/sup>C CMOS voltage reference based on compensated VTH with wide temperature range and high PSRR,\u201d 16th IEEE International New Circuits and Systems Conference (2018) 66 (DOI: 10.1109\/NEWCAS.2018.8585544).","DOI":"10.1109\/NEWCAS.2018.8585544"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] L. Magnelli, <i>et al<\/i>.: \u201cA 2.6nW, 0.45V temperature-compensated subthreshold CMOS voltage reference,\u201d IEEE J. Solid-State Circuits <b>46<\/b> (2011) 465 (DOI: 10.1109\/JSSC.2010.2092997).","DOI":"10.1109\/JSSC.2010.2092997"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] K. Ueno, <i>et al<\/i>.: \u201cA 300nW, 15ppm\/<sup>\u00b0<\/sup>C, 20ppm\/V CMOS voltage reference circuit consisting of subthreshold MOSFETs,\u201d IEEE J. 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Zhu, <i>et al<\/i>.: \u201cA -115dB PSRR CMOS bandgap reference with a novel voltage self-regulating technique,\u201d IEEE Proceedings of Custom Integrated Circuits Conference (2014) 1 (DOI: 10.1109\/CICC.2014.6946006).","DOI":"10.1109\/CICC.2014.6946006"},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] Z. Ning, <i>et al<\/i>.: \u201cA novel high PSR voltage reference with secondary temperature compensation,\u201d International Conference on Electrical and Control Engineering (2010) 3200 (DOI: 10.1109\/iCECE.2010.781).","DOI":"10.1109\/iCECE.2010.781"},{"key":"18","unstructured":"[18] W. Li, <i>et al<\/i>.: \u201cA low power CMOS bandgap voltage reference with enhanced power supply rejection,\u201d 8th IEEE International Conference (2009) 300 (DOI: 10.1109\/ASICON.2009.5351450)."},{"key":"19","doi-asserted-by":"crossref","unstructured":"[19] Y. Zeng, <i>et al<\/i>.: \u201cUltra-low-power, high PSRR CMOS voltage reference with negative feedback,\u201d IET Circuits, Devices Syst. <b>11<\/b> (2017) 535 (DOI: 10.1049\/iet-cds.2016.0452).","DOI":"10.1049\/iet-cds.2016.0452"},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] Y. Guoyi and Z. Xuecheng: \u201cA novel current reference based on subthreshold MOSFETs with high PSRR,\u201d Mecroelectronics Jounal <b>39<\/b> (2007) 1874 (DOI: 10.1016\/j.mejo.2007.09.015).","DOI":"10.1016\/j.mejo.2007.09.015"},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] Y. Chen, <i>et al.<\/i>: \u201cA 160-nA 0.00039%\/V all-MOSFET voltage reference with PSRR superior than -80dB up to 1GHz,\u201d 2019 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA) (2019) 41 (DOI: 10.1109\/ICTA48799.2019.9012844).","DOI":"10.1109\/ICTA48799.2019.9012844"},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] M. 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Xu, <i>et al.<\/i>: \u201cA novel 0.84ppm\/<sup>\u00b0<\/sup>C CMOS curvature-compensated bandgap with 1.2V supply voltage,\u201d AEU - International Journal of Electronics and Communications <b>91<\/b> (2018) 66 (DOI: 10.1016\/j.aeue.2018.05.001).","DOI":"10.1016\/j.aeue.2018.05.001"},{"key":"29","doi-asserted-by":"crossref","unstructured":"[29] Z. Ning, <i>et al.<\/i>: \u201cA novel high PSR voltage reference with secondary temperature compensation,\u201d International Conference on Electrical and Control Engineering (2010) 3200 (DOI: 10.1109\/iCECE.2010.781).","DOI":"10.1109\/iCECE.2010.781"},{"key":"30","doi-asserted-by":"crossref","unstructured":"[30] S. Yousefi and M. Jalali: \u201cA high-PSRR low-power CMOS voltage reference based on weighted VGS difference,\u201d AEU - International Journal of Electronics and Communications <b>70<\/b> (2016) 50 (DOI: 10.1016\/j.aeue.2015.09.019).","DOI":"10.1016\/j.aeue.2015.09.019"}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/19\/8\/19_19.20220009\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,30]],"date-time":"2022-04-30T05:04:43Z","timestamp":1651295083000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/19\/8\/19_19.20220009\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,4,25]]},"references-count":30,"journal-issue":{"issue":"8","published-print":{"date-parts":[[2022]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.19.20220009","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,4,25]]},"article-number":"19.20220009"}}