{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,25]],"date-time":"2025-10-25T19:11:59Z","timestamp":1761419519374},"reference-count":37,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"10","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2022,5,25]]},"DOI":"10.1587\/elex.19.20220089","type":"journal-article","created":{"date-parts":[[2022,4,11]],"date-time":"2022-04-11T22:09:10Z","timestamp":1649714950000},"page":"20220089-20220089","source":"Crossref","is-referenced-by-count":4,"title":["A bit-interleaving 12T bitcell with built-in write-assist for sub-threshold SRAM"],"prefix":"10.1587","volume":"19","author":[{"given":"Dashan","family":"Shi","sequence":"first","affiliation":[{"name":"Institute of Microelectronics of Chinese Academy of Sciences"},{"name":"University of Chinese Academy of Sciences"}]},{"given":"Jia","family":"Yuan","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of Chinese Academy of Sciences"}]},{"given":"Jialu","family":"Yin","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of Chinese Academy of Sciences"},{"name":"University of Chinese Academy of Sciences"}]},{"given":"Yulian","family":"Wang","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of Chinese Academy of Sciences"},{"name":"University of Chinese Academy of Sciences"}]},{"given":"Shushan","family":"Qiao","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of Chinese Academy of Sciences"},{"name":"University of Chinese Academy of Sciences"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] M. 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Solid-State Circuits <b>41<\/b> (2006) 146 (DOI: 10.1109\/JSSC.2005.859025).","DOI":"10.1109\/JSSC.2005.859025"}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/19\/10\/19_19.20220089\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,5,9]],"date-time":"2024-05-09T05:03:23Z","timestamp":1715231003000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/19\/10\/19_19.20220089\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,5,25]]},"references-count":37,"journal-issue":{"issue":"10","published-print":{"date-parts":[[2022]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.19.20220089","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,5,25]]},"article-number":"19.20220089"}}