{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,31]],"date-time":"2025-08-31T10:04:13Z","timestamp":1756634653192},"reference-count":31,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"13","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2022,7,10]]},"DOI":"10.1587\/elex.19.20220244","type":"journal-article","created":{"date-parts":[[2022,6,8]],"date-time":"2022-06-08T22:09:50Z","timestamp":1654726190000},"page":"20220244-20220244","source":"Crossref","is-referenced-by-count":3,"title":["A co-design method of customized ISA design space exploration and fixed-point library construction for RISC-V dedicated processor"],"prefix":"10.1587","volume":"19","author":[{"given":"Meng","family":"Liu","sequence":"first","affiliation":[{"name":"Faculty of Information Technology, School of Microelectronics, Beijing University of Technology"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] T. Kono, <i>et al.<\/i>: \u201cEssential roles, challenges and development of embedded MCU micro-systems to innovate edge computing for the IoT\/AI age,\u201d IEICE Trans. Electron. <b>E103-C<\/b> (2020) 132 (DOI: 10.1587\/transele.2019CDI0001).","DOI":"10.1587\/transele.2019CDI0001"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] A. Pullini, <i>et al.<\/i>: \u201cMr. Wolf: an energy-precision scalable parallel ultra low power SoC for IoT edge processing,\u201d IEEE J. Solid-State Circuits <b>54<\/b> (2019) 1970 (DOI: 10.1109\/JSSC.2019.2912307).","DOI":"10.1109\/JSSC.2019.2912307"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] T.-K. Chien, <i>et al.<\/i>: \u201cLow-power MCU with embedded ReRAM buffers as sensor hub for IoT applications,\u201d IEEE J. Emerg. Sel. Topics Circuits Syst. <b>6<\/b> (2016) 247 (DOI: 10.1109\/JETCAS.2016.2547778).","DOI":"10.1109\/JETCAS.2016.2547778"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] M. Sarmiento, <i>et al.<\/i>: \u201cA sub-\u00b5W reversed-body-bias 8-bit processor on 65-nm silicon-on-thin-box (SOTB) for IoT applications,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>68<\/b> (2021) 3182 (DOI: 10.1109\/TCSII.2021.3090102).","DOI":"10.1109\/TCSII.2021.3090102"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] S. Yuan, <i>et al.<\/i>: \u201cReal-time detection of hardware trojan attacks on general-purpose registers in a RISC-V processor,\u201d IEICE Electron. Express <b>18<\/b> (2021) 20210098 (DOI: 10.1587\/elex.18.20210098).","DOI":"10.1587\/elex.18.20210098"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] J. Kim, <i>et al.<\/i>: \u201cCID: co-architecting instruction cache and decompression system for embedded systems,\u201d IEEE Trans. Comput. <b>70<\/b> (2020) 1132 (DOI: 10.1109\/TC.2020.3010062).","DOI":"10.1109\/TC.2020.3010062"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] S. Greengard: \u201cWill RISC-V revolutionize computing?,\u201d Commun. ACM <b>63<\/b> (2020) 30 (DOI: 10.1145\/3386377).","DOI":"10.1145\/3386377"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] A. Garofalo, <i>et al.<\/i>: \u201cXpulpNN: enabling energy efficient and flexible inference of quantized neural networks on RISC-V based IoT end nodes,\u201d IEEE Trans. Emerg. Topics Comput. <b>9<\/b> (2021) 1489 (DOI: 10.1109\/TETC.2021.3072337).","DOI":"10.1109\/TETC.2021.3072337"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] F.J. Schuiki, <i>et al.<\/i>: \u201cStream semantic registers: a lightweight RISC-V ISA extension achieving full compute utilization in single-issue cores,\u201d IEEE Trans. Comput. <b>70<\/b> (2021) 212 (DOI: 0.1109\/TC.2020.2987314).","DOI":"10.1109\/TC.2020.2987314"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] C. Duran, <i>et al.<\/i>: \u201cAn energy-efficient RISC-V RV32IMAC microcontroller for periodical-driven sensing applications,\u201d IEEE Custom Integrated Circuits Conference (2020) 1 (DOI: 10.1109\/CICC48029.2020.9075877).","DOI":"10.1109\/CICC48029.2020.9075877"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] C. Duran, <i>et al.<\/i>: \u201cA 10pJ\/bit 256b AES-SoC exploiting memory access acceleration,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>69<\/b> (2022) 1612 (DOI: 10.1109\/TCSII.2021.3126984).","DOI":"10.1109\/TCSII.2021.3126984"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] T.T. Hoang, <i>et al.<\/i>: \u201cLow-power high-performance 32-bit RISC-V microcontroller on 65-nm silicon-on-thin-BOX (SOTB),\u201d IEICE Electron. Express <b>17<\/b> (2020) 20200282 (DOI: 110.1587\/elex.17.20200282).","DOI":"10.1587\/elex.17.20200282"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] S.Y. Lee, <i>et al.<\/i>: \u201cRISC-V CNN coprocessor for real-time epilepsy detection in wearable application,\u201d IEEE Trans. Biomed. Circuits Syst. <b>15<\/b> (2021) 679 (DOI: 10.1109\/TBCAS.2021.3092744).","DOI":"10.1109\/TBCAS.2021.3092744"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] S. Davidson, <i>et al.<\/i>: \u201cThe celerity open-source 511-core RISC-V tiered accelerator fabric: fast architectures and design methodologies for fast chips,\u201d IEEE Micro <b>38<\/b> (2018) 30 (DOI: 10.1109\/MM.2018.022071133).","DOI":"10.1109\/MM.2018.022071133"},{"key":"15","doi-asserted-by":"crossref","unstructured":"[15] P. Choi, <i>et al.<\/i>: \u201cArchitectural supports for block ciphers in a RISC CPU core by instruction overloading,\u201d IEEE Trans. Comput. <b>70<\/b> (2021) 1253 (DOI: 10.1109\/TC.2021.3066883).","DOI":"10.1109\/TC.2021.3050515"},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] V. Herdt, <i>et al.<\/i>: \u201cFast and accurate performance evaluation for RISC-V using virtual prototypes,\u201d Proc. of the Conference on Design, Automation and Test in Europe (DATE) (2020) 618 (DOI: 10.23919\/DATE48585.2020.9116522).","DOI":"10.23919\/DATE48585.2020.9116522"},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] M. Gautsch, <i>et al.<\/i>: \u201cNear-threshold RISC-V core with DSP extensions for scalable IoT endpoint devices,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>25<\/b> (2017) 2700 (DOI: 10.1109\/TVLSI.2017.2654506).","DOI":"10.1109\/TVLSI.2017.2654506"},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] C. Bai, <i>et al.<\/i>: \u201cBOOM-explorer: RISC-V BOOM microarchitecture design space exploration framework,\u201d IEEE\/ACM International Conference on Computer-Aided Design (2021) 1 (DOI: 10.1109\/ICCAD51958.2021.9643455).","DOI":"10.1109\/ICCAD51958.2021.9643455"},{"key":"19","doi-asserted-by":"crossref","unstructured":"[19] H. Geng, <i>et al.<\/i>: \u201cTechniques for CAD tool parameter auto-tuning in physical synthesis: a survey,\u201d Asia and South Pacific Design Automation Conference (ASP-DAC) (2022) 635 (DOI: 10.1109\/ASP-DAC52403.2022.9712495).","DOI":"10.1109\/ASP-DAC52403.2022.9712495"},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] J. Zhang, <i>et al.<\/i>: \u201cEasyMAC: design exploration-enabled multiplier-accumulator generator using a canonical architectural representation,\u201d Asia and South Pacific Design Automation Conference (ASP-DAC) (2022) 647 (DOI: 10.1109\/ASP-DAC52403.2022.9712519).","DOI":"10.1109\/ASP-DAC52403.2022.9712519"},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] Q. Sun, <i>et al.<\/i>: \u201cCorrelated multi-objective multi-fidelity optimization for HLS directives design,\u201d ACM Trans. Des. Autom. Electron. Syst. <b>27<\/b> (2022) 1 (DOI: 10.1145\/3503540).","DOI":"10.1145\/3503540"},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] H. Geng, <i>et al.<\/i>: \u201cHigh-speed adder design space exploration via graph neural processe,\u201d IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. (2021) 1 (DOI: 10.1109\/TCAD.2021.3114262).","DOI":"10.1109\/TCAD.2021.3114262"},{"key":"23","doi-asserted-by":"crossref","unstructured":"[23] T. Fritzmann, <i>et al.<\/i>: \u201cTowards reliable and secure post-quantum co-processors based on RISC-V,\u201d Proc. of the Conference on Design, Automation and Test in Europe (DATE) (2019) 1148 (DOI: 10.23919\/DATE.2019.8715173).","DOI":"10.23919\/DATE.2019.8715173"},{"key":"24","doi-asserted-by":"crossref","unstructured":"[24] R. Balas and L. Benini: \u201cRISC-V for real-time MCUs-software optimization and microarchitectural gap analysis,\u201d Proc. of the Conference on Design, Automation and Test in Europe (DATE) (2021) 874 (DOI: 10.23919\/DATE51398.2021.9474114).","DOI":"10.23919\/DATE51398.2021.9474114"},{"key":"25","doi-asserted-by":"crossref","unstructured":"[25] A. Kurth, <i>et al.<\/i>: \u201cAn open-source platform for high-performance non-coherent on-chip communication,\u201d IEEE Trans. Comput. (2021) 1 (DOI: 10.1109\/TC.2021.3107726).","DOI":"10.1109\/TC.2021.3107726"},{"key":"26","doi-asserted-by":"crossref","unstructured":"[26] N. Dao, <i>et al.<\/i>: \u201cFlexbex: a RISC-V with a reconfigurable instruction extension,\u201d Int. Conf. Field-Program. Technol. (ICFPT) (2020) 190 (DOI: 10.1109\/ICFPT51103.2020.00034).","DOI":"10.1109\/ICFPT51103.2020.00034"},{"key":"27","doi-asserted-by":"crossref","unstructured":"[27] L. Bertaccini, <i>et al.<\/i>: \u201cTiny-FPU: low-cost floating-point support for small RISC-V MCU cores,\u201d Int. Symp. Circuits and Systems (ISCAS) (2021) 1 (DOI: 10.1109\/ISCAS51556.2021.9401149).","DOI":"10.1109\/ISCAS51556.2021.9401149"},{"key":"28","doi-asserted-by":"crossref","unstructured":"[28] P.H.B. Amor, <i>et al.<\/i>: \u201cA RISC-V ISA extension for ultra-low power IoT wireless signal processing,\u201d IEEE Trans. Comput. <b>71<\/b> (2021) 766 (DOI: 110.1109\/TC.2021.3063027).","DOI":"10.1109\/TC.2021.3063027"},{"key":"29","doi-asserted-by":"crossref","unstructured":"[29] Z. Nikoli\u0107, <i>et al.<\/i>: \u201cDesign and implementation of numerical linear algebra algorithms on fixed point DSPs,\u201d EURASIP J. Advanc. Signal Processing <b>2007<\/b> (2007) 1 (DOI: 10.1155\/2007\/87046).","DOI":"10.1155\/2007\/87046"},{"key":"30","doi-asserted-by":"crossref","unstructured":"[30] E. Manor, <i>et al.<\/i>: \u201cORDIC hardware acceleration using DMA-based ISA extension,\u201d J. Low Power Electron. Appl. <b>12<\/b> (2022) 4 (DOI: 10.3390\/jlpea12010004).","DOI":"10.3390\/jlpea12010004"},{"key":"31","doi-asserted-by":"crossref","unstructured":"[31] K.D. Nguyen, <i>et al.<\/i>: \u201cA trigonometric hardware acceleration in 32-bit RISC-V microcontroller with custom instruction,\u201d IEICE Electron. Express <b>18<\/b> (2021) 20210266 (DOI: 10.1587\/elex.18.20210266).","DOI":"10.1587\/elex.18.20210266"}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/19\/13\/19_19.20220244\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,16]],"date-time":"2022-07-16T04:27:40Z","timestamp":1657945660000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/19\/13\/19_19.20220244\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,7,10]]},"references-count":31,"journal-issue":{"issue":"13","published-print":{"date-parts":[[2022]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.19.20220244","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,7,10]]},"article-number":"19.20220244"}}