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Abdel-Hafeez and S. Harb: \u201cA VLSI high-performance priority encoder using standard CMOS library,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>53<\/b> (2006) 597 (DOI: 10.1109\/TCSII.2006.876412).","DOI":"10.1109\/TCSII.2006.876412"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] K. Lahiri, <i>et al<\/i>.: \u201cThe LOTTERYBUS on-chip communication architecture,\u201d IEEE Trans. Very Lagre Scale Integr. (VLSI) Syst. <b>14<\/b> (2006) 596 (DOI: 10.1109\/TVLSI.2006.878210).","DOI":"10.1109\/TVLSI.2006.878210"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] K. Sekar, <i>et al<\/i>.: \u201cDynamically configurable bus topologies for high-performance on-chip communication,\u201d IEEE Trans. Very Lagre Scale Integr. (VLSI) Syst. <b>16<\/b> (2008) 1413 (DOI: 10.1109\/TVLSI.2008.2000727).","DOI":"10.1109\/TVLSI.2008.2000727"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] K.A. Helal, <i>et al<\/i>.: \u201cPriority-select arbiter: an efficient round-robin arbiter,\u201d 2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS) (2015) 1 (DOI: 10.1109\/NEWCAS.2015.7182062).","DOI":"10.1109\/NEWCAS.2015.7182062"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] R. Dobkin, <i>et al<\/i>.: \u201cQNoC asynchronous router with dynamic virtual channel allocation,\u201d NOCS (2007) 218 (DOI: 10.1109\/NOCS.2007.36).","DOI":"10.1109\/NOCS.2007.36"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] T. Singh and A. Taubin: \u201cA highly scalable GALS crossbar using token ring arbitration,\u201d IEEE Des. Test Comput. <b>24<\/b> (2007) 464 (DOI: 10.1109\/MDT.2007.150).","DOI":"10.1109\/MDT.2007.150"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] J. Pontes, <i>et al<\/i>.: \u201cHermes-AA: a 65nm asynchronous NoC router with adaptive routing,\u201d SOCC (2010) 493 (DOI: 10.1109\/SOCC.2010.5784676).","DOI":"10.1109\/SOCC.2010.5784676"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] W. Jiang and S.M. Nowick: \u201cA high-throughput asynchronous multi-resource arbiter using a pipelined assignment approach,\u201d 23rd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) (2017) 1 (DOI: 10.1109\/ASYNC.2017.21).","DOI":"10.1109\/ASYNC.2017.21"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] T.J. Chaney and C.E. Molnar: \u201cAnomalous behavior of synchronizer and arbiter circuits,\u201d IEEE Trans. Comput. <b>22<\/b> (1973) 421 (DOI: 10.1109\/T-C.1973.223730).","DOI":"10.1109\/T-C.1973.223730"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] D.J. Kinniment and J.V. Woods: \u201cSynchronisation and arbitration circuits in digital systems,\u201d Proceedings of the Institution of Electrical Engineers (1976) 961 (DOI: 10.1049\/piee.1976.0212).","DOI":"10.1049\/piee.1976.0212"},{"key":"11","unstructured":"[11] C. Seitz: \u201c<i>Ideas about Arbiters<\/i>,\u201d Lambda (1980) 10."},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] L.A. Plana, <i>et al<\/i>.: \u201cSpiNNaker: design and implementation of a GALS multicore system-on-chip,\u201d J. Emerg. Technol. Comput. Syst. <b>7<\/b> (2011) 18 (DOI: 10.1145\/2043643.2043647).","DOI":"10.1145\/2043643.2043647"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] Y. Thonnart, <i>et al<\/i>.: \u201cA fully-asynchronous low-power framework for GALS NoC integration,\u201d 2010 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (2010) 33 (DOI: 10.1109\/DATE.2010.5457239).","DOI":"10.1109\/DATE.2010.5457239"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] A. Taubin, <i>et al<\/i>.: \u201cDesign automation of real-life asynchronous devices and systems,\u201d Foundations and Trends\u00aein Electronic Design Automation <b>2<\/b> (2007) 1 (DOI: 10.1561\/1000000006).","DOI":"10.1561\/1000000006"},{"key":"15","doi-asserted-by":"crossref","unstructured":"[15] W.W. Plummer: \u201cAsynchronous arbiters,\u201d IEEE Trans. Comput. <b>21<\/b> (1972) 37 (DOI: 10.1109\/t-c.1972.223429).","DOI":"10.1109\/T-C.1972.223429"},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] R.C. Pearce, <i>et al<\/i>.: \u201cAsynchronous arbiter module,\u201d IEEE Trans. Comput. <b>24<\/b> (1975) 931 (DOI: 10.1109\/T-C.1972.223429).","DOI":"10.1109\/T-C.1975.224339"},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] A. Yakovlev, <i>et al<\/i>.: \u201cA low latency asynchronous arbitration circuit,\u201d IEEE Trans. Very Lagre Scale Integr. (VLSI) Syst. <b>2<\/b> (1994) 372 (DOI: 10.1109\/92.311648).","DOI":"10.1109\/92.311648"},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] M.B. Josephs and J.T. Yantchev: \u201cCMOS design of the tree arbiter element,\u201d IEEE Trans. Very Lagre Scale Integr. (VLSI) Syst. <b>4<\/b> (1996) 472 (DOI: 10.1109\/92.544412).","DOI":"10.1109\/92.544412"},{"key":"19","doi-asserted-by":"crossref","unstructured":"[19] S.R. Naqvi and A. Steininger: \u201cA tree arbiter cell for high speed resource sharing in asynchronous environments,\u201d 2014 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE) (2014) 1 (DOI: 10.7873\/DATE.2014.308).","DOI":"10.7873\/DATE.2014.308"},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] A. Ghiribaldi, <i>et al<\/i>.: \u201cA transition-signaling bundled data NoC switch architecture for cost-effective GALS multicore systems,\u201d 2013 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE) (2013) 332 (DOI: 10.7873\/DATE.2013.079).","DOI":"10.7873\/DATE.2013.079"},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] G. Miorandi, <i>et al<\/i>.: \u201cIncreasing impartiality and robustness in high-performance N-way asynchronous arbiters,\u201d 2015 21st IEEE International Symposium on Asynchronous Circuits and Systems (2015) 108 (DOI: 10.1109\/ASYNC.2015.24).","DOI":"10.1109\/ASYNC.2015.24"},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] T. Turko, <i>et al<\/i>.: \u201cAn asynchronous fixed priority arbiter for high througput time correlated single photon counting systems,\u201d 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS) (2018) 765 (DOI: 10.1109\/ICECS.2018.8618023).","DOI":"10.1109\/ICECS.2018.8618023"},{"key":"23","doi-asserted-by":"crossref","unstructured":"[23] G.A. Subbarao and P.D. H\u00e4fliger: \u201cDesign and comparison of synthesizable fair asynchronous arbiter,\u201d 2020 18th IEEE International New Circuits and Systems Conference (NEWCAS) (2020) 122 (DOI: 10.1109\/NEWCAS49341.2020.9159757).","DOI":"10.1109\/NEWCAS49341.2020.9159757"},{"key":"24","doi-asserted-by":"crossref","unstructured":"[24] M. Imai and T. Yoneda: \u201cNovel implementation method of multiple-way asynchronous arbiters,\u201d IEICE Trans. Fundamentals <b>E98-A<\/b> (2015) 1519 (DOI: 10.1587\/transfun.E98.A.1519).","DOI":"10.1587\/transfun.E98.A.1519"},{"key":"25","unstructured":"[25] K. van Berkel, <i>et al<\/i>.: \u201cStretching quasi delay insensitivity by means of extended isochronic forks,\u201d Proceedings Second Working Conference on Asynchronous Design Methodologies (1995) 99 (DOI: 10.1109\/wcadm.1995.514647)."},{"key":"26","doi-asserted-by":"crossref","unstructured":"[26] J. Spars and S. Furber: <i>Principles Asynchronous Circuit Design<\/i> (Kluwer Academic Publishers, 2002) (DOI: 10.1007\/978-1-4757-3385-3).","DOI":"10.1007\/978-1-4757-3385-3"},{"key":"27","doi-asserted-by":"crossref","unstructured":"[27] A. Semenov, <i>et al<\/i>.: \u201cSynthesis of speed-independent circuits from STG-unfolding segment,\u201d Proceedings of the 34th Design Automation Conference (1997) 16 (DOI: 10.1145\/266021.266028).","DOI":"10.1145\/266021.266028"},{"key":"28","doi-asserted-by":"crossref","unstructured":"[28] L. Kleeman and A. Cantoni: \u201cMetastable behavior in digital systems,\u201d IEEE Des. Test Comput. <b>4<\/b> (1987) 4 (DOI: 10.1109\/MDT.1987.295189).","DOI":"10.1109\/MDT.1987.295189"},{"key":"29","doi-asserted-by":"crossref","unstructured":"[29] S. Yang and M.R. Greenstreet: \u201cSimulating improbable events,\u201d 2007 44th ACM\/IEEE Design Automation Conference (2007) 154 (DOI: 10.1145\/1278480.1278518).","DOI":"10.1109\/DAC.2007.375143"},{"key":"30","doi-asserted-by":"crossref","unstructured":"[30] S. Hauck: \u201cAsynchronous design methodologies: an overview,\u201d Proc. IEEE <b>83<\/b> (1995) 69 (DOI: 10.1109\/5.362752).","DOI":"10.1109\/5.362752"}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/19\/19\/19_19.20220265\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,5,10]],"date-time":"2024-05-10T04:27:45Z","timestamp":1715315265000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/19\/19\/19_19.20220265\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,10,10]]},"references-count":30,"journal-issue":{"issue":"19","published-print":{"date-parts":[[2022]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.19.20220265","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,10,10]]},"article-number":"19.20220265"}}