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Razavi: \u201cThe flash ADC,\u201d IEEE Solid-State Circuits Mag. <b>9<\/b> (2017) 9 (DOI: 10.1109\/MSSC.2017.2712998).","DOI":"10.1109\/MSSC.2017.2712998"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] S. Chaudhary and R. Pandey: \u201cHigh-speed, low-power and low-offset fully differential double-tail dynamic comparator using charge sharing technique,\u201d S\u0101dhan\u0101 <b>45<\/b> (2020) 1 (DOI: 10.1007\/s12046-020-01344-y).","DOI":"10.1007\/s12046-020-01344-y"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] P.P. Gandhi and N.M. Devashrayee: \u201cA novel low offset low power CMOS dynamic comparator,\u201d Analog Integrated Circuits and Signal Processing <b>96<\/b> (2018) 147 (DOI: 10.1007\/S10470-018-1166-9).","DOI":"10.1007\/s10470-018-1166-9"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] V. Katyal, <i>et al.<\/i>: \u201cA new high precision low offset dynamic comparator for high resolution high speed ADCs,\u201d APCCAS 2006-2006 IEEE Asia Pacific Conference on Circuits and Systems (2006) 5 (DOI: 10.1109\/APCCAS.2006.342249).","DOI":"10.1109\/APCCAS.2006.342249"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] B.-M. Min, <i>et al.<\/i>: \u201cA 69-mW 10-bit 80-Msample\/s pipelined CMOS ADC,\u201d IEEE J. Solid-State Circuits <b>38<\/b> (2003) 2031 (DOI: 10.1109\/JSSC.2003.819166).","DOI":"10.1109\/JSSC.2003.819166"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] T.B. Cho and P.R. Gray: \u201cA 10 b, 20Msample\/s, 35mW pipeline A\/D converter,\u201d IEEE J. Solid-State Circuits <b>30<\/b> (1995) 166 (DOI: 10.1109\/4.364429).","DOI":"10.1109\/4.364429"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] J. D\u00edaz-Madrid, <i>et al.<\/i>: \u201cA low kickback fully differential dynamic comparator for pipeline analog-to-digital converters,\u201d Engineering Reports <b>1<\/b> (2019) (DOI: 10.1002\/eng2.12055).","DOI":"10.1002\/eng2.12055"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] S.M. Lee, <i>et al.<\/i>: \u201cEnhanced input range dynamic comparator for pipeline analogue-to-digital converter,\u201d Electronics Letters <b>45<\/b> (2009) 728 (DOI: 10.1049\/EL.2009.0005).","DOI":"10.1049\/el.2009.0005"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] T. Kobayashi, <i>et al.<\/i>: \u201cA current-controlled latch sense amplifier and a static power-saving input buffer for low-power architecture,\u201d IEEE J. Solid-State Circuits <b>28<\/b> (1993) 523 (DOI: 10.1109\/4.210039).","DOI":"10.1109\/4.210039"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] D. Schinkel, <i>et al.<\/i>: \u201cA double-tail latch-type voltage sense amplifier with 18ps setup+hold time,\u201d 2007 IEEE International Solid-State Circuits Conference. Dig. Tech. Papers (2007) 314 (DOI: 10.1109\/ISSCC.2007.373420).","DOI":"10.1109\/ISSCC.2007.373420"},{"key":"15","doi-asserted-by":"crossref","unstructured":"[15] X. Tang, <i>et al.<\/i>: \u201cAn energy-efficient comparator with dynamic floating inverter amplifier,\u201d IEEE J. Solid-State Circuits <b>55<\/b> (2020) 1011 (DOI: 10.1109\/JSSC.2019.2960485).","DOI":"10.1109\/JSSC.2019.2960485"},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] H.S. Bindra, <i>et al.<\/i>: \u201cA 1.2-V dynamic bias latch-type comparator in 65-nm CMOS with 0.4-mV input noise,\u201d IEEE J. Solid-State Circuits <b>53<\/b> (2018) 1902 (DOI: 10.1109\/JSSC.2018.2820147).","DOI":"10.1109\/JSSC.2018.2820147"},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] A. Khorami, <i>et al.<\/i>: \u201cA low-power high-speed comparator for precise applications,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>26<\/b> (2018) 2038 (DOI: 10.1109\/TVLSI.2018.2833037).","DOI":"10.1109\/TVLSI.2018.2833037"},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] Z. Li, <i>et al.<\/i>: \u201cA low-power low-noise dynamic comparator with latch-embedding floating amplifier,\u201d 2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) (2020) 39 (DOI: 10.1109\/APCCAS50809.2020.9301705).","DOI":"10.1109\/APCCAS50809.2020.9301705"},{"key":"19","doi-asserted-by":"crossref","unstructured":"[19] A. Alshehri, <i>et al.<\/i>: \u201cStrongARM latch comparator performance enhancement by implementing clocked forward body biasing,\u201d 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS) (2018) 229 (DOI: 10.1109\/ICECS.2018.8617903).","DOI":"10.1109\/ICECS.2018.8617903"},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] A.T. Ramkaj, <i>et al.<\/i>: \u201cA 13.5-Gb\/s 5-mV-sensitivity 26.8-ps-CLK-OUT delay triple-latch feedforward dynamic comparator in 28-nm CMOS,\u201d IEEE Solid-State Circuits Lett. <b>2<\/b> (2019) 167 (DOI: 10.1109\/LSSC.2019.2936152).","DOI":"10.1109\/LSSC.2019.2936152"},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] S. Babayan-Mashhadi and R. Lotfi: \u201cAnalysis and design of a low-voltage low-power double-tail comparator,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>22<\/b> (2014) 343 (DOI: 10.1109\/TVLSI.2013.2241799).","DOI":"10.1109\/TVLSI.2013.2241799"},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] V. Savani and N.M. Devashrayee: \u201cDesign and analysis of low-power high-speed shared charge reset technique based dynamic latch comparator,\u201d Microelectron. J. <b>74<\/b> (2018) 116 (DOI: 10.1016\/j.mejo.2018.01.020).","DOI":"10.1016\/j.mejo.2018.01.020"},{"key":"23","doi-asserted-by":"crossref","unstructured":"[23] M. Tohidi, <i>et al.<\/i>: \u201cLow-power comparator in 65-nm CMOS with reduced delay time,\u201d 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS) (2016) 736 (DOI: 10.1109\/ICECS.2016.7841307).","DOI":"10.1109\/ICECS.2016.7841307"},{"key":"24","doi-asserted-by":"crossref","unstructured":"[24] B.-J. Kuo, <i>et al.<\/i>: \u201cA 0.6V, 1.3GHz dynamic comparator with cross-coupled latches,\u201d VLSI Design, Automation and Test (VLSI-DAT) (2015) 1 (DOI: 10.1109\/VLSI-DAT.2015.7114523).","DOI":"10.1109\/VLSI-DAT.2015.7114523"},{"key":"25","unstructured":"[25] P.E. Allen and D.R. Holberg: <i>CMOS Analog Circuit Design<\/i>, Publishing House of Electronics Industry, 2007."},{"key":"26","doi-asserted-by":"crossref","unstructured":"[26] R.K. Siddharth, <i>et al.<\/i>: \u201cA 1-V, 3-GHz strong-arm latch voltage comparator for high speed applications,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>67<\/b> (2020) 2918 (DOI: 10.1109\/TCSII.2020.2993064).","DOI":"10.1109\/TCSII.2020.2993064"},{"key":"27","doi-asserted-by":"crossref","unstructured":"[27] M. Miyahara and A. Matsuzawa: \u201cA low-offset latched comparator using zero-static power dynamic offset cancellation technique,\u201d 2009 IEEE Asian Solid-State Circuits Conference (2009) 233 (DOI: 10.1109\/ASSCC.2009.5357221).","DOI":"10.1109\/ASSCC.2009.5357221"},{"key":"28","doi-asserted-by":"crossref","unstructured":"[28] J. Kim, <i>et al.<\/i>: \u201cSimulation and analysis of random decision errors in clocked comparators,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>56<\/b> (2009) 1844 (DOI: 10.1109\/TCSI.2009.2028449).","DOI":"10.1109\/TCSI.2009.2028449"},{"key":"29","doi-asserted-by":"crossref","unstructured":"[29] T. Sepke, <i>et al.<\/i>: \u201cNoise analysis for comparator-based circuits,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>56<\/b> (2009) 541 (DOI: 10.1109\/TCSI.2008.2002547).","DOI":"10.1109\/TCSI.2008.2002547"},{"key":"30","doi-asserted-by":"crossref","unstructured":"[30] A. Nikoozadeh and B. Murmann: \u201cAn analysis of latch comparator offset due to load capacitor mismatch,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>53<\/b> (2006) 1398 (DOI: 10.1109\/TCSII.2006.883204).","DOI":"10.1109\/TCSII.2006.883204"},{"key":"31","doi-asserted-by":"crossref","unstructured":"[31] R. Hogervorst, <i>et al.<\/i>: \u201cCMOS low-voltage operational amplifiers with constant-gm rail-to-rail input stage,\u201d Analog Integr. Circ. Sig. Process. <b>5<\/b> (1994) 135 (DOI: 10.1007\/BF01272648).","DOI":"10.1007\/BF01272648"},{"key":"32","doi-asserted-by":"crossref","unstructured":"[32] J.H. Botma, <i>et al.<\/i>: \u201cRail-to-rail constant-gm input stage and class AB output stage for low-voltage CMOS op amps,\u201d Analog Integr. Circ. Sig. Process. <b>6<\/b> (1994) 121 (DOI: 10.1007\/BF01239246).","DOI":"10.1007\/BF01239246"}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/19\/16\/19_19.20220274\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,8,27]],"date-time":"2022-08-27T04:28:01Z","timestamp":1661574481000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/19\/16\/19_19.20220274\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,8,25]]},"references-count":32,"journal-issue":{"issue":"16","published-print":{"date-parts":[[2022]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.19.20220274","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,8,25]]},"article-number":"19.20220274"}}